Virtualization Multiprocessor ID Register
Holds the value of the Virtualization Multiprocessor ID. This is the value returned by Non-secure EL1 reads of MPIDR, which in a multiprocessor system, provides an additional PE identification system.
AArch32 System register VMPIDR bits [31:0] are architecturally mapped to AArch64 System register VMPIDR_EL2[31:0].
This register is present only when FEAT_AA32EL2 is implemented. Otherwise, direct accesses to VMPIDR are UNDEFINED.
If EL2 is not implemented but EL3 is implemented, this register takes the value of the MPIDR.
VMPIDR is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| M | U | RES0 | MT | Aff2 | Aff1 | Aff0 | |||||||||||||||||||||||||
Indicates whether this implementation includes the functionality introduced by the Armv7 Multiprocessing Extensions.
| M | Meaning |
|---|---|
| 0b0 |
This implementation does not include the Armv7 Multiprocessing Extensions functionality. |
| 0b1 |
This implementation includes the Armv7 Multiprocessing Extensions functionality. |
Access to this field is RES1 .
Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system.
| U | Meaning |
|---|---|
| 0b0 |
Processor is part of a multiprocessor system. |
| 0b1 |
Processor is part of a uniprocessor system. |
The reset behavior of this field is:
Reserved, RES0.
Indicates whether the lowest level of affinity consists of logical PEs that are implemented using a multithreading type approach. See the description of Aff0 for more information about affinity levels.
| MT | Meaning |
|---|---|
| 0b0 |
Performance of PEs at the lowest affinity level is largely independent. |
| 0b1 |
Performance of PEs at the lowest affinity level is very interdependent. |
The reset behavior of this field is:
Affinity level 2. See the description of Aff0 for more information.
The reset behavior of this field is:
Affinity level 1. See the description of Aff0 for more information.
The reset behavior of this field is:
Affinity level 0. The value of the MPIDR.{Aff2, Aff1, Aff0} or MPIDR_EL1.{Aff3, Aff2, Aff1, Aff0} set of fields of each PE must be unique within the system as a whole.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
(coproc = 0b1111, opc1 = 0b100, CRn = 0b0000, CRm = 0b0000, opc2 = 0b101)
if !IsFeatureImplemented(FEAT_AA32EL2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T0 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then R(t) = VMPIDR(); elsif PSTATE.EL == EL3 then if SCR().NS == '0' then Undefined(); elsif !HaveEL(EL2) then R(t) = MPIDR(); else R(t) = VMPIDR(); end; end;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
(coproc = 0b1111, opc1 = 0b100, CRn = 0b0000, CRm = 0b0000, opc2 = 0b101)
if !IsFeatureImplemented(FEAT_AA32EL2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T0 == '1' then AArch32_TakeHypTrapException(0x03); else Undefined(); end; elsif PSTATE.EL == EL2 then VMPIDR() = R(t); elsif PSTATE.EL == EL3 then if SCR().NS == '0' then Undefined(); elsif !HaveEL(EL2) then return; else VMPIDR() = R(t); end; end;
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
(coproc = 0b1111, opc1 = 0b000, CRn = 0b0000, CRm = 0b0000, opc2 = 0b101)
if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T0 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) then R(t) = VMPIDR_EL2()[31:0]; elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) then R(t) = VMPIDR(); else R(t) = MPIDR(); end; elsif PSTATE.EL == EL2 then R(t) = MPIDR(); elsif PSTATE.EL == EL3 then R(t) = MPIDR(); end;
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