VMPIDR_EL2

AArch64 System register VMPIDR_EL2 bits [31:0] are architecturally mapped to AArch32 System register VMPIDR[31:0].

This register is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to VMPIDR_EL2 are UNDEFINED.

If EL2 is not implemented, reads of this register return the value of the MPIDR_EL1 and writes to the register are ignored.

This register has no effect if EL2 is not enabled in the current Security state.

Attributes

Field descriptions

Bits [63:40]:

Aff3, bits [39:32]:

Bit [31]:

U, bit [30]:

Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system.

U	Meaning
0b0	Processor is part of a multiprocessor system.
0b1	Processor is part of a uniprocessor system.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [29:25]:

MT, bit [24]:

Indicates whether the lowest level of affinity consists of logical PEs that are implemented using a multithreading type approach. See the description of VMPIDR_EL2.Aff0 for more information about affinity levels.

MT	Meaning
0b0	Performance of PEs at the lowest affinity level is largely independent.
0b1	Performance of PEs at the lowest affinity level is very interdependent.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Aff2, bits [23:16]:

Aff1, bits [15:8]:

Aff0, bits [7:0]:

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, VMPIDR_EL2

(op0 = 0b11, op1 = 0b100, CRn = 0b0000, CRm = 0b0000, op2 = 0b101)

if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x050); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = VMPIDR_EL2(); elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then X{64}(t) = MPIDR_EL1(); else X{64}(t) = VMPIDR_EL2(); end; end;

MSR VMPIDR_EL2, <Xt>

(op0 = 0b11, op1 = 0b100, CRn = 0b0000, CRm = 0b0000, op2 = 0b101)

if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x050) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then VMPIDR_EL2() = X{64}(t); elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then return; else VMPIDR_EL2() = X{64}(t); end; end;

MRS <Xt>, MPIDR_EL1

(op0 = 0b11, op1 = 0b000, CRn = 0b0000, CRm = 0b0000, op2 = 0b101)

if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then AArch64_SystemAccessTraptoEL1orEL2(0x18); else Undefined(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().MPIDR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() then X{64}(t) = VMPIDR_EL2(); else X{64}(t) = MPIDR_EL1(); end; elsif PSTATE.EL == EL2 then X{64}(t) = MPIDR_EL1(); elsif PSTATE.EL == EL3 then X{64}(t) = MPIDR_EL1(); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																								Aff3
RES1	U	RES0					MT	Aff2								Aff1								Aff0

Configuration

Attributes

Field descriptions

Bits [63:40]:

Aff3, bits [39:32]:

Bit [31]:

U, bit [30]:

Bits [29:25]:

MT, bit [24]:

Aff2, bits [23:16]:

Aff1, bits [15:8]:

Aff0, bits [7:0]:

Access Instructions