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DLR: Debug Link Register

Purpose

In Debug state, holds the address to restart from.

Configuration

AArch32 System register DLR bits [31:0] are architecturally mapped to AArch64 System register DLR_EL0[31:0].

This register is present only when FEAT_AA32 is implemented. Otherwise, direct accesses to DLR are UNDEFINED.

Attributes

DLR is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
ADDR

ADDR, bits [31:0]

Restart address.

Accessing DLR

Accesses to this register use the following encodings in the System register encoding space:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11110b0110b01000b01010b001

if !IsFeatureImplemented(FEAT_AA32) then UNDEFINED; elsif !Halted() then UNDEFINED; else R[t] = DLR;

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11110b0110b01000b01010b001

if !IsFeatureImplemented(FEAT_AA32) then UNDEFINED; elsif !Halted() then UNDEFINED; else DLR = R[t];