CMPLO (vectors)

Compare unsigned lower than vector, setting the condition flags

Compare active unsigned integer elements in the first source vector being lower than corresponding unsigned elements in the second source vector, and place the boolean results of the comparison in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.

This is a pseudo-instruction of CMP<cc> (vectors). This means:

The encodings in this description are named to match the encodings of CMP<cc> (vectors).
The assembler syntax is used only for assembly, and is not used on disassembly.
The description of CMP<cc> (vectors) gives the operational pseudocode, any constrained unpredictable behavior, and any operational information for this instruction.

Higher

(FEAT_SVE || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	1	0	0	1	0	0	size		0	Zm					0	0	0	Pg			Zn					1	Pd
																op		o2									ne

Encoding

CMPLO <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>

is equivalent to

CMPHI <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>

Assembler Symbols

<Pd>	Is the name of the destination scalable predicate register, encoded in the "Pd" field.

<T>

Is the size specifier, encoded in size:

size	<T>
00	B
01	H
10	S
11	D

<Pg>	Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zm>	Is the name of the second source scalable vector register, encoded in the "Zm" field.

<Zn>	Is the name of the first source scalable vector register, encoded in the "Zn" field.

Operation

The description of CMP<cc> (vectors) gives the operational pseudocode for this instruction.

CMPLO (vectors)

Higher(FEAT_SVE || FEAT_SME)

Encoding

Assembler Symbols

Operation

Higher

(FEAT_SVE || FEAT_SME)