Contains the sampled CONTEXTIDR_EL1 and VMID values that are captured on reading PMU.PMPCSR.
This register is present only when FEAT_PMUv3_EXT64 is implemented and FEAT_PCSRv8p2 is implemented. Otherwise, direct accesses to PMVCIDSR are RES0.
If FEAT_PMUv3_EXT32 is implemented, the same content is present in the same location, and can be accessed using PMVIDSR[31:0] and PMCID1SR[31:0].
Before Armv8.2, the PC Sample-based Profiling Extension can be implemented in the external debug register space, as indicated by the value of EDDEVID.PCSample.
PMVCIDSR is a 64-bit register.
This register is part of the PMU block.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | VMID[15:8] | VMID | |||||||||||||||||||||||||||||
CONTEXTIDR_EL1 |
Reserved, RES0.
Extension to VMID[7:0]. For more information, see VMID[7:0].
The reset behavior of this field is:
Reserved, RES0.
VMID sample. The VMID associated with the most recent PMU.PMPCSR sample. When the most recent PMU.PMPCSR sample was generated:
Because the value written to PMVIDSR is an indirect read of the VMID value, it is CONSTRAINED UNPREDICTABLE whether PMVIDSR is set to the original or new value if PMU.PMPCSR samples:
The reset behavior of this field is:
Context ID. The value of CONTEXTIDR that is associated with the most recent PMU.PMPCSR sample. When the most recent PMU.PMPCSR sample is generated:
Because the value written to this register is an indirect read of CONTEXTIDR, it is CONSTRAINED UNPREDICTABLE whether this register is set to the original or new value if PMU.PMPCSR samples:
The reset behavior of this field is:
IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN'.
Accesses to this register use the following encodings:
Accessible at offset 0x208 from PMU