Holds the base address of the translation table for the initial lookup for stage 2 of an address translation in the Non-secure PL1&0 translation regime, and other information for this translation regime.
AArch32 System register VTTBR bits [63:0] are architecturally mapped to AArch64 System register VTTBR_EL2[63:0].
This register is present only when EL2 is capable of using AArch32. Otherwise, direct accesses to VTTBR are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
VTTBR is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | VMID | BADDR | |||||||||||||||||||||||||||||
| BADDR | CnP | ||||||||||||||||||||||||||||||
Reserved, RES0.
The VMID for the translation table.
The reset behavior of this field is:
Translation table base address, bits[47:x], Bits [x-1:1] are RES0, with the additional requirement that if bits[x-1:3] are not all zero, this is a misaligned translation table base address, with effects that are CONSTRAINED UNPREDICTABLE, and must be one of the following:
x is determined from the value of VTCR.SL0 and VTCR.T0SZ as follows:
If bits[47:40] of the translation table base address are not zero, an Address size fault is generated.
The reset behavior of this field is:
Common not Private. This bit indicates whether each entry that is pointed to by VTTBR is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of VTTBR.CnP is 1.
| CnP | Meaning |
|---|---|
| 0b0 |
The translation table entries pointed to by VTTBR are permitted to differ from the entries for VTTBR for other PEs in the Inner Shareable domain. This is not affected by the value of the current VMID. |
| 0b1 |
The translation table entries pointed to by VTTBR are the same as the translation table entries for every other PE in the Inner Shareable domain for which the value of VTTBR.CnP is 1 and the VMID is the same as the current VMID. |
When a TLB combines entries from stage 1 translation and stage 2 translation into a single entry, that entry can only be shared between different PEs if the value of the CnP bit is 1 for both stage 1 and stage 2.
If the value of the VTTBR.CnP bit is 1 on multiple PEs in the same Inner Shareable domain and those VTTBRs do not point to the same translation table entries when the VMID value is the same as the current VMID, then the results of translations are CONSTRAINED UNPREDICTABLE, see 'CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values'.
The reset behavior of this field is:
Reserved, RES0.
Accesses to this register use the following encodings in the System register encoding space:
MRRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm>
| coproc | CRm | opc1 |
|---|---|---|
| 0b1111 | 0b0010 | 0b0110 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T2 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T2 == '1' then AArch32.TakeHypTrapException(0x04); else UNDEFINED; elsif PSTATE.EL == EL2 then (R[t2], R[t]) = (VTTBR<63:32>, VTTBR<31:0>); elsif PSTATE.EL == EL3 then if SCR.NS == '0' then UNDEFINED; else (R[t2], R[t]) = (VTTBR<63:32>, VTTBR<31:0>);
MCRR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm>
| coproc | CRm | opc1 |
|---|---|---|
| 0b1111 | 0b0010 | 0b0110 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T2 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T2 == '1' then AArch32.TakeHypTrapException(0x04); else UNDEFINED; elsif PSTATE.EL == EL2 then VTTBR = R[t2]:R[t]; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then UNDEFINED; else VTTBR = R[t2]:R[t];