Configures event counter n, where n is 0 to 30.
External register PMEVTYPER<n>_EL0 bits [31:0] are architecturally mapped to AArch64 System register PMEVTYPER<n>_EL0[31:0].
External register PMEVTYPER<n>_EL0 bits [63:32] are architecturally mapped to AArch64 System register PMEVTYPER<n>_EL0[63:32] when FEAT_PMUv3_TH is implemented, or FEAT_PMUv3p8 is implemented or FEAT_PMUv3_EXT64 is implemented.
External register PMEVTYPER<n>_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMEVTYPER<n>[31:0].
This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMEVTYPER<n>_EL0 are RES0.
PMEVTYPER<n>_EL0 is in the Core power domain.
If event counter n is not implemented:
PMEVTYPER<n>_EL0 is a 64-bit register.
This register is part of the PMU block.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TC | TE | RES0 | SYNC | VS | TLC | RES0 | TH | ||||||||||||||||||||||||
P | U | NSK | NSU | NSH | M | MT | SH | T | RLK | RLU | RLH | RES0 | evtCount[15:10] | evtCount[9:0] |
Threshold Control. Defines the threshold function. In the description of this field:
TC | Meaning |
---|---|
0b000 |
Not-equal. The counter increments by VB[n] on each processor cycle when VB[n] is not equal to TH[n]. |
0b001 |
Not-equal, count. The counter increments by 1 on each processor cycle when VB[n] is not equal to TH[n]. |
0b010 |
Equals. The counter increments by VB[n] on each processor cycle when VB[n] is equal to TH[n]. |
0b011 |
Equals, count. The counter increments by 1 on each processor cycle when VB[n] is equal to TH[n]. |
0b100 |
Greater-than-or-equal. The counter increments by VB[n] on each processor cycle when VB[n] is greater than or equal to TH[n]. |
0b101 |
Greater-than-or-equal, count. The counter increments by 1 on each processor cycle when VB[n] is greater than or equal to TH[n]. |
0b110 |
Less-than. The counter increments by VB[n] on each processor cycle when VB[n] is less than TH[n]. |
0b111 |
Less-than, count. The counter increments by 1 on each processor cycle when VB[n] is less than TH[n]. |
Comparisons treat VB[n] and TH[n] as unsigned integer values.
On each processor cycle when the condition specified by PMEVTYPER<n>_EL0.TC[2:1] is true:
On each processor cycle when the condition specified by PMEVTYPER<n>_EL0.TC[2:1] is false:
If PMEVTYPER<n>_EL0.{TC, TLC, TH} are zero then the threshold function is disabled.
The reset behavior of this field is:
Threshold Control. Defines the threshold function. In the description of this field:
TC | Meaning |
---|---|
0b000 |
Not-equal. The counter increments by V[n-1] on each processor cycle when VB[n] is not equal to TH[n]. |
0b010 |
Equals. The counter increments by V[n-1] on each processor cycle when VB[n] is equal to TH[n]. |
0b100 |
Greater-than-or-equal. The counter increments by V[n-1] on each processor cycle when VB[n] is greater than or equal to TH[n]. |
0b110 |
Less-than. The counter increments by V[n-1] on each processor cycle when VB[n] is less than TH[n]. |
All other values are reserved.
Comparisons treat VB[n] and TH[n] as unsigned integer values.
On each processor cycle when the condition specified by PMEVTYPER<n>_EL0.TC is true, the counter increments by V[n-1].
On each processor cycle when the condition specified by PMEVTYPER<n>_EL0.TC is false, the counter does not increment.
The reset behavior of this field is:
Threshold Control. Defines the threshold function. In the description of this field:
TC | Meaning |
---|---|
0b001 |
Equal to not-equal. The counter increments on each processor cycle when VB[n] is not equal to TH[n] and VB[n] was equal to TH[n] on the previous processor cycle. |
0b010 | Equal to/from not-equal. The counter increments on each processor cycle when either:
|
0b011 |
Not-equal to equal. The counter increments on each processor cycle when VB[n] is equal to TH[n] and VB[n] was not equal to TH[n] on the previous processor cycle. |
0b101 |
Less-than to greater-than-or-equal. The counter increments on each processor cycle when VB[n] is greater than or equal to TH[n] and VB[n] was less than TH[n] on the previous processor cycle. |
0b110 | Less-than to/from greater-than-or-equal. The counter increments on each processor cycle when either:
|
0b111 |
Greater-than-or-equal to less-than. The counter increments on each processor cycle when VB[n] is less than TH[n] and VB[n] was greater than or equal to TH[n] on the previous processor cycle. |
All other values are reserved.
Comparisons treat VB[n] and TH[n] as unsigned integer values.
On each processor cycle when the condition specified by PMEVTYPER<n>_EL0.TC is true:
On each processor cycle when the condition specified by PMEVTYPER<n>_EL0.TC is false, the counter does not increment.
The reset behavior of this field is:
Reserved, RES0.
Threshold Edge. Enables the edge condition. When PMEVTYPER<n>_EL0.TE is 1, the event counter increments on cycles when the result of the threshold condition changes. See PMEVTYPER<n>_EL0.TC for more information.
TE | Meaning |
---|---|
0b0 |
Threshold edge condition disabled. |
0b1 |
Threshold edge condition enabled. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Synchronous mode. Controls whether a PMU exception generated by the counter is synchronous or asynchronous.
SYNC | Meaning |
---|---|
0b0 |
Asynchronous PMU exception is enabled. |
0b1 |
Synchronous PMU exception is enabled. |
The reset behavior of this field is:
Reserved, RES0.
SVE mode filtering. Controls counting events in Streaming and Non-streaming SVE modes.
VS | Meaning |
---|---|
0b00 |
This mechanism has no effect on the filtering of events. |
0b01 |
The PE does not count events in Streaming SVE mode. |
0b10 |
The PE does not count events in Non-streaming SVE mode. |
All other values are reserved.
The reset behavior of this field is:
Reserved, RES0.
Threshold Linking Control. Extends PMEVTYPER<n>_EL0.TC with additional controls for event linking. See PMEVTYPER<n>_EL0.TC.
TLC | Meaning |
---|---|
0b00 |
Threshold linking disabled. |
0b01 |
Threshold linking enabled. If the threshold condition described by PMEVTYPER<n>_EL0.TC is false, the counter increments by V[n-1]. Otherwise, the counter increments as described by PMEVTYPER<n>_EL0.TC. |
0b10 |
Threshold linking enabled. If the threshold condition described by PMEVTYPER<n>_EL0.TC is false, the counter increments by V[n-1]. Otherwise, the counter does not increment. |
All other values are reserved.
See PMEVTYPER<n>_EL0.TC for more information
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Threshold value. Provides the unsigned value for the threshold function defined by PMEVTYPER<n>_EL0.TC.
If PMEVTYPER<n>_EL0.{TC, TH} are both zero and either FEAT_PMUv3_TH2 is not implemented or PMEVTYPER<n>_EL0.TLC is also zero, then the threshold function is disabled.
If PMU.PMMIR_EL1.THWIDTH is less than 12, then bits PMEVTYPER<n>_EL0.TH[11:UInt(PMU.PMMIR_EL1.THWIDTH)] are RES0. This accounts for the behavior when writing a value greater-than-or-equal-to 2UInt(PMU.PMMIR_EL1.THWIDTH).
The reset behavior of this field is:
Reserved, RES0.
EL1 filtering. Controls counting events in EL1.
P | Meaning |
---|---|
0b0 |
This mechanism has no effect on filtering of events. |
0b1 |
The PE does not count events in EL1. |
If Secure and Non-secure states are implemented, then counting events in Non-secure EL1 is further controlled by PMEVTYPER<n>_EL0.NSK.
If FEAT_RME is implemented, then counting events in Realm EL1 is further controlled by PMEVTYPER<n>_EL0.RLK.
If EL3 is implemented, then counting events in EL3 is further controlled by PMEVTYPER<n>_EL0.M.
The reset behavior of this field is:
EL0 filtering. Controls counting events in EL0.
U | Meaning |
---|---|
0b0 |
This mechanism has no effect on filtering of events. |
0b1 |
The PE does not count events in EL0. |
If Secure and Non-secure states are implemented, then counting events in Non-secure EL0 is further controlled by PMEVTYPER<n>_EL0.NSU.
If FEAT_RME is implemented, then counting events in Realm EL0 is further controlled by PMEVTYPER<n>_EL0.RLU.
The reset behavior of this field is:
Non-secure EL1 filtering. Controls counting events in Non-secure EL1. If PMEVTYPER<n>_EL0.NSK is not equal to PMEVTYPER<n>_EL0.P, then the PE does not count events in Non-secure EL1. Otherwise, this mechanism has no effect on filtering of events in Non-secure EL1.
NSK | Meaning |
---|---|
0b0 | When PMEVTYPER<n>_EL0.P == 0, this mechanism has no effect on filtering of events. When PMEVTYPER<n>_EL0.P == 1, the PE does not count events in Non-secure EL1. |
0b1 | When PMEVTYPER<n>_EL0.P == 0, the PE does not count events in Non-secure EL1. When PMEVTYPER<n>_EL0.P == 1, this mechanism has no effect on filtering of events. |
The reset behavior of this field is:
Reserved, RES0.
Non-secure EL0 filtering. Controls counting events in Non-secure EL0. If PMEVTYPER<n>_EL0.NSU is not equal to PMEVTYPER<n>_EL0.U, then the PE does not count events in Non-secure EL0. Otherwise, this mechanism has no effect on filtering of events in Non-secure EL0.
NSU | Meaning |
---|---|
0b0 | When PMEVTYPER<n>_EL0.U == 0, this mechanism has no effect on filtering of events. When PMEVTYPER<n>_EL0.U == 1, the PE does not count events in Non-secure EL0. |
0b1 | When PMEVTYPER<n>_EL0.U == 0, the PE does not count events in Non-secure EL0. When PMEVTYPER<n>_EL0.U == 1, this mechanism has no effect on filtering of events. |
The reset behavior of this field is:
Reserved, RES0.
EL2 filtering. Controls counting events in EL2.
NSH | Meaning |
---|---|
0b0 |
The PE does not count events in EL2. |
0b1 |
This mechanism has no effect on filtering of events. |
If EL3 is implemented and FEAT_SEL2 is implemented, then counting events in Secure EL2 is further controlled by PMEVTYPER<n>_EL0.SH.
If FEAT_RME is implemented, then counting events in Realm EL2 is further controlled by PMEVTYPER<n>_EL0.RLH.
The reset behavior of this field is:
Reserved, RES0.
EL3 filtering. Controls counting events in EL3. If PMEVTYPER<n>_EL0.M is not equal to PMEVTYPER<n>_EL0.P, then the PE does not count events in EL3. Otherwise, this mechanism has no effect on filtering of events in EL3.
M | Meaning |
---|---|
0b0 | When PMEVTYPER<n>_EL0.P == 0, this mechanism has no effect on filtering of events. When PMEVTYPER<n>_EL0.P == 1, the PE does not count events in EL3. |
0b1 | When PMEVTYPER<n>_EL0.P == 0, the PE does not count events in EL3. When PMEVTYPER<n>_EL0.P == 1, this mechanism has no effect on filtering of events. |
The reset behavior of this field is:
Reserved, RES0.
Multithreading.
MT | Meaning |
---|---|
0b0 |
Count events only on controlling PE. |
0b1 |
Count events from any PE with the same affinity at level 1 and above as this PE. |
From Armv8.6, the IMPLEMENTATION DEFINED multi-threaded PMU extension is not permitted, meaning if FEAT_MTPMU is not implemented, this field is RES0. See ID_AA64DFR0_EL1.MTPMU.
This field is ignored by the PE and treated as zero when FEAT_MTPMU is implemented and disabled.
The reset behavior of this field is:
Reserved, RES0.
Secure EL2 filtering. Controls counting events in Secure EL2. If PMEVTYPER<n>_EL0.SH is equal to PMEVTYPER<n>_EL0.NSH, then the PE does not count events in Secure EL2. Otherwise, this mechanism has no effect on filtering of events in Secure EL2.
SH | Meaning |
---|---|
0b0 | When PMEVTYPER<n>_EL0.NSH == 0, the PE does not count events in Secure EL2. When PMEVTYPER<n>_EL0.NSH == 1, this mechanism has no effect on filtering of events. |
0b1 | When PMEVTYPER<n>_EL0.NSH == 0, this mechanism has no effect on filtering of events. When PMEVTYPER<n>_EL0.NSH == 1, the PE does not count events in Secure EL2. |
The reset behavior of this field is:
When Secure EL2 is not implemented, access to this field is RES0.
Reserved, RES0.
Non-Transactional state filtering bit. Controls counting of events in Non-transactional state.
T | Meaning |
---|---|
0b0 |
This bit has no effect on the filtering of events. |
0b1 |
Do not count Attributable events in Non-transactional state. |
For each Unattributable event, it is IMPLEMENTATION DEFINED whether the filtering applies.
The reset behavior of this field is:
Reserved, RES0.
Realm EL1 filtering. Controls counting events in Realm EL1. If PMEVTYPER<n>_EL0.RLK is not equal to PMEVTYPER<n>_EL0.P, then the PE does not count events in Realm EL1. Otherwise, this mechanism has no effect on filtering of events in Realm EL1.
RLK | Meaning |
---|---|
0b0 | When PMEVTYPER<n>_EL0.P == 0, this mechanism has no effect on filtering of events. When PMEVTYPER<n>_EL0.P == 1, the PE does not count events in Realm EL1. |
0b1 | When PMEVTYPER<n>_EL0.P == 0, the PE does not count events in Realm EL1. When PMEVTYPER<n>_EL0.P == 1, this mechanism has no effect on filtering of events. |
The reset behavior of this field is:
Reserved, RES0.
Realm EL0 filtering. Controls counting events in Realm EL0. If PMEVTYPER<n>_EL0.RLU is not equal to PMEVTYPER<n>_EL0.U, then the PE does not count events in Realm EL0. Otherwise, this mechanism has no effect on filtering of events in Realm EL0.
RLU | Meaning |
---|---|
0b0 | When PMEVTYPER<n>_EL0.U == 0, this mechanism has no effect on filtering of events. When PMEVTYPER<n>_EL0.U == 1, the PE does not count events in Realm EL0. |
0b1 | When PMEVTYPER<n>_EL0.U == 0, the PE does not count events in Realm EL0. When PMEVTYPER<n>_EL0.U == 1, this mechanism has no effect on filtering of events. |
The reset behavior of this field is:
Reserved, RES0.
Realm EL2 filtering. Controls counting events in Realm EL2. If PMEVTYPER<n>_EL0.RLH is equal to PMEVTYPER<n>_EL0.NSH, then the PE does not count events in Realm EL2. Otherwise, this mechanism has no effect on filtering of events in Realm EL2.
RLH | Meaning |
---|---|
0b0 | When PMEVTYPER<n>_EL0.NSH == 0, the PE does not count events in Realm EL2. When PMEVTYPER<n>_EL0.NSH == 1, this mechanism has no effect on filtering of events. |
0b1 | When PMEVTYPER<n>_EL0.NSH == 0, this mechanism has no effect on filtering of events. When PMEVTYPER<n>_EL0.NSH == 1, the PE does not count events in Realm EL2. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Extension to evtCount[9:0]. For more information, see evtCount[9:0].
The reset behavior of this field is:
Reserved, RES0.
Event to count.
The event number of the event that is counted by event counter PMU.PMEVCNTR<n>_EL0.
The ranges of event numbers allocated to each type of event are shown in 'Allocation of the PMU event number space'.
If FEAT_PMUv3p8 is implemented and PMEVTYPER<n>_EL0.evtCount is programmed to an event that is reserved or not supported by the PE, no events are counted and the value returned by a direct or external read of the PMEVTYPER<n>_EL0.evtCount field is the value written to the field.
Arm recommends this behavior for all implementations of FEAT_PMUv3.
Otherwise, if PMEVTYPER<n>_EL0.evtCount is programmed to an event that is reserved or not supported by the PE, the behavior depends on the value written:
UNPREDICTABLE means the event must not expose privileged information.
The reset behavior of this field is:
If FEAT_PMUv3_EXT32 is implemented, and at least one of FEAT_PMUv3_TH or FEAT_PMUv3p8 is implemented, then bits [63:32] of this register are accessible at offset 0xA00 + (4*n). Otherwise accesses at this offset are IMPLEMENTATION DEFINED.
SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
Accesses to this register use the following encodings:
When FEAT_PMUv3_EXT64 is implemented[63:0] Accessible at offset 0x400 + (8 * n) from PMU
[31:0] Accessible at offset 0x400 + (4 * n) from PMU
[63:32] Accessible at offset 0xA00 + (4 * n) from PMU