Controls the corresponding Single-shot Comparator Control resource.
External register TRCSSCCR<n> bits [31:0] are architecturally mapped to AArch64 System register TRCSSCCR<n>[31:0].
This register is present only when FEAT_ETE is implemented, FEAT_TRC_EXT is implemented and UInt(TRCIDR4.NUMSSCC) > n. Otherwise, direct accesses to TRCSSCCR<n> are RES0.
TRCSSCCR<n> is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | RST | ARC[7] | ARC[6] | ARC[5] | ARC[4] | ARC[3] | ARC[2] | ARC[1] | ARC[0] | SAC[15] | SAC[14] | SAC[13] | SAC[12] | SAC[11] | SAC[10] | SAC[9] | SAC[8] | SAC[7] | SAC[6] | SAC[5] | SAC[4] | SAC[3] | SAC[2] | SAC[1] | SAC[0] |
Reserved, RES0.
Selects the Single-shot Comparator Control mode.
RST | Meaning |
---|---|
0b0 |
The Single-shot Comparator Control is in single-shot mode. |
0b1 |
The Single-shot Comparator Control is in multi-shot mode. |
The reset behavior of this field is:
Selects one or more Address Range Comparators for Single-shot control.
ARC[<m>] | Meaning |
---|---|
0b0 |
The Address Range Comparator <m>, is not selected for Single-shot control. |
0b1 |
The Address Range Comparator <m>, is selected for Single-shot control. |
The reset behavior of this field is:
Accessing this field has the following behavior:
Selects one or more Single Address Comparators for Single-shot control.
SAC[<m>] | Meaning |
---|---|
0b0 |
The Single Address Comparator <m>, is not selected for Single-shot control. |
0b1 |
The Single Address Comparator <m>, is selected for Single-shot control. |
The reset behavior of this field is:
Accessing this field has the following behavior:
Must be programmed if any TRCRSCTLR<a>.GROUP == 0b0011 and TRCRSCTLR<a>.SINGLE_SHOT[n] == 1.
Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.
Component | Offset | Instance |
---|---|---|
ETE | 0x280 + (4 * n) | TRCSSCCR<n> |
This interface is accessible as follows: