Main control register 2 for the debug implementation.
External register EDSCR2 bits [31:0] are architecturally mapped to AArch64 System register MDSCR_EL1[63:32].
EDSCR2 is in the Core power domain.
This register is present only when FEAT_Debugv8p9 is implemented or FEAT_TRBE_EXT is implemented. Otherwise, direct accesses to EDSCR2 are RES0.
EDSCR2 is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | EHBWE | RES0 | TTA | RES0 | |||||||||||||||||||||||||||
Reserved, RES0.
Extended Halting Breakpoint and Watchpoint Enable. Enables use of additional breakpoints or watchpoints.
| EHBWE | Meaning |
|---|---|
| 0b0 |
Halting disabled for Breakpoint and Watchpoint debug events generated by each breakpoint <n> and Watchpoint <n>, where n is greater than or equal to 16. |
| 0b1 |
Breakpoints and Watchpoint debug events are not affected by this mechanism. |
When OSLSR_EL1.OSLK is 1, this field can be read and written through the MDSCR_EL1 System register.
It is IMPLEMENTATION DEFINED whether this field is implemented or is RES0 when 16 or fewer breakpoints are implemented, 16 or fewer watchpoints are implemented, and MDSELR_EL1 is implemented as RAZ/WI.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Trap Trace Accesses.
Traps access to the following System registers:
AArch64: TRBBASER_EL1, TRBIDR_EL1, TRBLIMITR_EL1, TRBMAR_EL1, TRBMPAM_EL1, TRBPTR_EL1, TRBSR_EL1, TRBTRG_EL1, TRCACATR<n>, TRCACVR<n>, TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1, TRCCIDCVR<n>, TRCCLAIMCLR, TRCCLAIMSET, TRCCNTCTLR<n>, TRCCNTRLDVR<n>, TRCCNTVR<n>, TRCCONFIGR, TRCDEVARCH, TRCDEVID, TRCEVENTCTL0R, TRCEVENTCTL1R, TRCEXTINSELR<n>, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4, TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12, TRCIDR13, TRCIMSPEC0, TRCIMSPEC<n>, TRCITEEDCR, TRCOSLSR, TRCPRGCTLR, TRCQCTLR, TRCRSCTLR<n>, TRCRSR, TRCSEQEVR<n>, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCR<n>, TRCSSCSR<n>, TRCSSPCICR<n>, TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR, TRCVMIDCCTLR0, TRCVMIDCCTLR1, and TRCVMIDCVR<n>.
| TTA | Meaning |
|---|---|
| 0b0 |
Accesses to trace System registers do not generate a Software Access debug event. |
| 0b1 |
Accesses to trace System registers generate a Software Access debug event, if OSLSR_EL1.OSLK is 0 and if halting is allowed. |
When OSLSR_EL1.OSLK is 1, this field can be read and written through the MDSCR_EL1 System register.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
| Component | Offset | Instance |
|---|---|---|
| Debug | 0x028 | EDSCR2 |
This interface is accessible as follows: