EDDFR1: External Debug Feature Register 1

Purpose

Provides top level information about the debug system in AArch64.

Configuration

There are no configuration notes.

Attributes

EDDFR1 is a 64-bit register.

Field descriptions

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABL_CMPs								DPFZS				EBEP				ITE				ABLE				PMICNTR				SPMU
CTX_CMPs								WRPs								BRPs								SYSPMUID

ABL_CMPs, bits [63:56]

When FEAT_ABLE is implemented:

Number of breakpoints that support address linking, minus 1. Defined values are:

ABL_CMPs	Meaning
0x00..0x3F	Number of breakpoints that support address linking minus 1.

All other values are reserved.

The number of breakpoints that support address linking is never more than either the number of breakpoints or the number of watchpoints.

Otherwise:

Reserved, RES0.

DPFZS, bits [55:52]

This field either has the same value as ID_AA64DFR1_EL1.DPFZS or reads as zero.

EBEP, bits [51:48]

This field either has the same value as ID_AA64DFR1_EL1.EBEP or reads as zero.

ITE, bits [47:44]

This field either has the same value as ID_AA64DFR1_EL1.ITE or reads as zero.

ABLE, bits [43:40]

Address Breakpoint Linking Extension. Defined values are:

ABLE	Meaning
0b0000	Address Breakpoint Linking Extension not implemented.
0b0001	Address Breakpoint Linking Extension implemented.

All other values are reserved.

FEAT_BWE implements the address range breakpoints and mismatch breakpoints part of the functionality identified by the value 0b0001.

FEAT_ABLE implements the functionality identified by the value 0b0001.

In an implementation that supports AArch64, this field has the same value as ID_AA64DFR1_EL1.ABLE.

PMICNTR, bits [39:36]

This field either has the same value as ID_AA64DFR1_EL1.PMICNTR or reads as zero.

SPMU, bits [35:32]

This field either has the same value as ID_AA64DFR1_EL1.SPMU or reads as zero.

CTX_CMPs, bits [31:24]

Context-aware breakpoints. Defined values are:

CTX_CMPs	Meaning
0x00	EDDFR.CTX_CMPs is the number of context-aware breakpoints, minus 1.
0x01..0x3F	Number of context-aware breakpoints minus 1.

All other values are reserved.

The value of this field is never greater than EDDFR1.BRPs.

In an implementation that supports AArch64, this field has the same value as ID_AA64DFR1_EL1.CTX_CMPs.

WRPs, bits [23:16]

Watchpoints. Defined values are:

WRPs	Meaning
0x00	EDDFR.WRPs is the number of watchpoints, minus 1.
0x01..0x3F	Number of watchpoints minus 1.

All other values are reserved.

In an implementation that supports AArch64, this field has the same value as ID_AA64DFR1_EL1.WRPs.

BRPs, bits [15:8]

Breakpoints. Defined values are:

BRPs	Meaning
0x00	EDDFR.BRPs is the number of breakpoints, minus 1.
0x01..0x3F	Number of breakpoints minus 1.

All other values are reserved.

In an implementation that supports AArch64, this field has the same value as ID_AA64DFR1_EL1.BRPs.

SYSPMUID, bits [7:0]

This field either has the same value as ID_AA64DFR1_EL1.SYSPMUID or reads as zero.

Accessing EDDFR1

EDDFR1 can be accessed through the external debug interface:

Component	Offset	Instance
Debug	0xD48	EDDFR1

This interface is accessible as follows:

When IsCorePowered(), !DoubleLockStatus() and (!IsZero(EDDFR1) or !OSLockStatus()), accesses to this register are RO.
When FEAT_DoPD is implemented and !IsCorePowered(), accesses to this register generate an error response.
Otherwise, accesses to this register are IMPDEF.

EDDFR1: External Debug Feature Register 1

Purpose

Configuration

Attributes

Field descriptions

ABL_CMPs, bits [63:56]When FEAT_ABLE is implemented:

Otherwise:

DPFZS, bits [55:52]

EBEP, bits [51:48]

ITE, bits [47:44]

ABLE, bits [43:40]

PMICNTR, bits [39:36]

SPMU, bits [35:32]

CTX_CMPs, bits [31:24]

WRPs, bits [23:16]

BRPs, bits [15:8]

SYSPMUID, bits [7:0]

Accessing EDDFR1

EDDFR1 can be accessed through the external debug interface:

ABL_CMPs, bits [63:56]

When FEAT_ABLE is implemented: