Provides top level information about the debug system in AArch64.
There are no configuration notes.
ID_AA64DFR1_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ABL_CMPs | DPFZS | EBEP | ITE | ABLE | PMICNTR | SPMU | |||||||||||||||||||||||||
| CTX_CMPs | WRPs | BRPs | SYSPMUID | ||||||||||||||||||||||||||||
Number of breakpoints that support address linking, minus 1.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| ABL_CMPs | Meaning |
|---|---|
| 0x00..0x3F |
Number of breakpoints that support address linking minus 1. |
All other values are reserved.
The number of breakpoints that support address linking is never more than either the number of breakpoints or the number of watchpoints.
Access to this field is RO.
Reserved, RES0.
Behavior of the cycle counter when event counting is frozen by a Statistical Profiling management event.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| DPFZS | Meaning |
|---|---|
| 0b0000 |
The cycle counter PMCCNTR_EL0 is never affected by PMCR_EL0.FZS. |
| 0b0001 |
The cycle counter PMCCNTR_EL0 does not count when PMCR_EL0.DP is 1 and counting by event counters accessible to EL1 is frozen by the PMCR_EL0.FZS mechanism. |
FEAT_SPE_DPFZS implements the functionality identified by the value 0b0001.
Access to this field is RO.
Exception-based event profiling.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| EBEP | Meaning |
|---|---|
| 0b0000 |
Exception-based event profiling not implemented. |
| 0b0001 |
Exception-based event profiling implemented. |
All other values are reserved.
FEAT_EBEP implements the functionality identified by the value 0b0001.
Access to this field is RO.
Instrumentation Trace Extension.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| ITE | Meaning |
|---|---|
| 0b0000 |
Instrumentation Trace Extension not implemented. |
| 0b0001 |
Instrumentation Trace Extension implemented. |
All other values are reserved.
FEAT_ITE implements the functionality identified by the value 0b0001.
Access to this field is RO.
Address Breakpoint Linking Extension. Defined values are:
| ABLE | Meaning |
|---|---|
| 0b0000 |
Address Breakpoint Linking Extension not implemented. |
| 0b0001 |
Address Breakpoint Linking Extension implemented. |
All other values are reserved.
FEAT_BWE implements the address range breakpoints and mismatch breakpoints part of the functionality identified by the value 0b0001.
FEAT_ABLE implements the functionality identified by the value 0b0001.
PMU fixed-function instruction counter.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| PMICNTR | Meaning |
|---|---|
| 0b0000 |
PMU fixed-function instruction counter not implemented. |
| 0b0001 |
PMU fixed-function instruction counter implemented. |
All other values are reserved.
FEAT_PMUv3_ICNTR implements the functionality identified by the value 0b0001.
If FEAT_PMUv3 is not implemented, then the only permitted value is 0b0000.
Access to this field is RO.
System PMU extension.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| SPMU | Meaning |
|---|---|
| 0b0000 |
System PMU extension not implemented. |
| 0b0001 |
System PMU extension implemented. |
| 0b0010 |
As 0b0001, and adds support for SPMZR_EL0. |
All other values are reserved.
FEAT_SPMU implements the functionality identified by the value 0b0001.
FEAT_SPMU2 implements the functionality identified by the value 0b0010.
From Armv9.5, the value 0b0001 is not permitted.
Access to this field is RO.
Context-aware breakpoints.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| CTX_CMPs | Meaning |
|---|---|
| 0x00 |
ID_AA64DFR0_EL1.CTX_CMPs is the number of context-aware breakpoints, minus 1. |
| 0x01..0x3F |
Number of context-aware breakpoints minus 1. |
All other values are reserved.
The value of this field is never greater than ID_AA64DFR1_EL1.BRPs.
Access to this field is RO.
Watchpoints.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| WRPs | Meaning |
|---|---|
| 0x00 |
ID_AA64DFR0_EL1.WRPs is the number of watchpoints, minus 1. |
| 0x01..0x3F |
Number of watchpoints minus 1. |
All other values are reserved.
Access to this field is RO.
Breakpoints.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| BRPs | Meaning |
|---|---|
| 0x00 |
ID_AA64DFR0_EL1.BRPs is the number of breakpoints, minus 1. |
| 0x01..0x3F |
Number of breakpoints minus 1. |
All other values are reserved.
Access to this field is RO.
System PMU ID. Indicates the largest value that can be written to SPMSELR_EL0.SYSPMUSEL.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| SYSPMUID | Meaning |
|---|---|
| 0x00..0x1F |
The largest supported value that can be written to SPMSELR_EL0.SYSPMUSEL. |
All other values are reserved.
Since System PMUs might not be contiguously accessible, this field does not necessarily indicate the total number of accessible System PMUs.
Access to this field is RO.
Reserved, RES0.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ID_AA64DFR1_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0000 | 0b0101 | 0b001 |
if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = ID_AA64DFR1_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = ID_AA64DFR1_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ID_AA64DFR1_EL1;