Provides information about implemented PE features.
The register mnemonic, EDAA32PFR, is derived from previous definitions of this register that defined this register only when AArch64 was not supported.
For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.
There are no configuration notes.
EDAA32PFR is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | MSA_frac | EL3 | EL2 | PMSA | VMSA |
Reserved, RES0.
Memory System Architecture fractional field. This holds the information on additional Memory System Architectures supported.
The value of this field is an IMPLEMENTATION DEFINED choice of:
MSA_frac | Meaning |
---|---|
0b0001 |
PMSAv8-64 supported in all translation regimes. VMSAv8-64 not supported. |
0b0010 |
PMSAv8-64 supported in all translation regimes. In addition to PMSAv8-64, stage 1 EL1&0 translation regime also supports VMSAv8-64. |
All other values are reserved.
Access to this field is RO.
Reserved, RES0.
AArch32 EL3 Exception level handling.
The value of this field is an IMPLEMENTATION DEFINED choice of:
EL3 | Meaning |
---|---|
0b0000 |
EL3 is not implemented or can be executed in AArch64 state. |
0b0001 |
EL3 can be executed in AArch32 state only. |
All other values are reserved.
EDPFR.{EL1, EL0} indicate whether EL1 and EL0 can only be executed in AArch32 state.
Access to this field is RO.
Reserved, RAZ.
AArch32 EL2 Exception level handling.
The value of this field is an IMPLEMENTATION DEFINED choice of:
EL2 | Meaning |
---|---|
0b0000 |
EL2 is not implemented or can be executed in AArch64 state. |
0b0001 |
EL2 can be executed in AArch32 state only. |
All other values are reserved.
EDPFR.{EL1, EL0} indicate whether EL1 and EL0 can only be executed in AArch32 state.
Access to this field is RO.
Reserved, RAZ.
Indicates support for a 32-bit PMSA.
The value of this field is an IMPLEMENTATION DEFINED choice of:
PMSA | Meaning |
---|---|
0b0000 |
PMSA-32 not supported. |
0b0100 |
PMSAv8-32 supported. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0000.
Access to this field is RO.
Indicates support for a VMSA in addition to a 32-bit PMSA.
VMSA | Meaning |
---|---|
0b0000 |
VMSA not supported. |
All other values are reserved.
Access to this field is RO.
The value of this field is an IMPLEMENTATION DEFINED choice of:
VMSA | Meaning |
---|---|
0b0000 |
VMSAv8-64 supported. |
0b1111 |
Memory system architecture described by EDAA32PFR.MSA_frac. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0000.
Access to this field is RO.
Reserved, RAZ.
Component | Offset | Instance |
---|---|---|
Debug | 0xD60 | EDAA32PFR |
This interface is accessible as follows: