Provides information about implemented PE features.
For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.
There are no configuration notes.
EDPFR is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UNKNOWN | AMU | UNKNOWN | SEL2 | SVE | |||||||||||||||||||||||||||
UNKNOWN | GIC | AdvSIMD | FP | EL3 | EL2 | EL1 | EL0 |
Reserved, UNKNOWN.
Indicates support for Activity Monitors Extension.
The value of this field is an IMPLEMENTATION DEFINED choice of:
AMU | Meaning |
---|---|
0b0000 |
Activity Monitors Extension is not implemented. |
0b0001 |
FEAT_AMUv1 is implemented. |
0b0010 |
FEAT_AMUv1p1 is implemented. As 0b0001 and adds support for virtualization of the activity monitor event counters. |
All other values are reserved.
FEAT_AMUv1 implements the functionality identified by the value 0b0001.
FEAT_AMUv1p1 implements the functionality identified by the value 0b0010.
In Armv8.0, the only permitted value is 0b0000.
In Armv8.4, the permitted values are 0b0000 and 0b0001.
From Armv8.6, the permitted values are 0b0000, 0b0001, and 0b0010.
Access to this field is RO.
Reserved, UNKNOWN.
Secure EL2.
The value of this field is an IMPLEMENTATION DEFINED choice of:
SEL2 | Meaning |
---|---|
0b0000 |
Secure EL2 is not implemented. |
0b0001 |
Secure EL2 is implemented. |
All other values are reserved.
Access to this field is RO.
Scalable Vector Extension.
The value of this field is an IMPLEMENTATION DEFINED choice of:
SVE | Meaning |
---|---|
0b0000 |
SVE is not implemented. |
0b0001 |
SVE is implemented. |
All other values are reserved.
Access to this field is RO.
Reserved, UNKNOWN.
System register GIC interface support.
The value of this field is an IMPLEMENTATION DEFINED choice of:
GIC | Meaning |
---|---|
0b0000 |
GIC CPU interface system registers not implemented. |
0b0001 |
System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. |
0b0011 |
System register interface to version 4.1 of the GIC CPU interface is supported. |
All other values are reserved.
In an Armv8-A implementation that supports AArch64, this field returns the value of ID_AA64PFR0_EL1.GIC.
Access to this field is RO.
Advanced SIMD.
The value of this field is an IMPLEMENTATION DEFINED choice of:
AdvSIMD | Meaning |
---|---|
0b0000 | Advanced SIMD is implemented, including support for the following SISD and SIMD operations:
|
0b0001 |
As for 0b0000, and also includes support for half-precision floating-point arithmetic. |
0b1111 |
Advanced SIMD is not implemented. |
All other values are reserved.
This field must have the same value as the FP field.
The permitted values are:
In an Armv8-A implementation that supports AArch64, this field returns the value of ID_AA64PFR0_EL1.AdvSIMD.
Access to this field is RO.
Floating-point.
The value of this field is an IMPLEMENTATION DEFINED choice of:
FP | Meaning |
---|---|
0b0000 | Floating-point is implemented, and includes support for:
|
0b0001 |
As for 0b0000, and also includes support for half-precision floating-point arithmetic. |
0b1111 |
Floating-point is not implemented. |
All other values are reserved.
This field must have the same value as the AdvSIMD field.
The permitted values are:
In an Armv8-A implementation that supports AArch64, this field returns the value of ID_AA64PFR0_EL1.FP.
Access to this field is RO.
AArch64 EL3 Exception level handling.
The value of this field is an IMPLEMENTATION DEFINED choice of:
EL3 | Meaning |
---|---|
0b0000 |
EL3 is not implemented or cannot be executed in AArch64 state. |
0b0001 |
EL3 can be executed in AArch64 state only. |
0b0010 |
EL3 can be executed in both Execution states. |
When the value of EDAA32PFR.EL3 is nonzero, this field must be 0b0000.
All other values are reserved.
In an Armv8-A implementation that supports AArch64, this field returns the value of ID_AA64PFR0_EL1.EL3.
Access to this field is RO.
AArch64 EL2 Exception level handling.
The value of this field is an IMPLEMENTATION DEFINED choice of:
EL2 | Meaning |
---|---|
0b0000 |
EL2 is not implemented or cannot be executed in AArch64 state. |
0b0001 |
EL2 can be executed in AArch64 state only. |
0b0010 |
EL2 can be executed in both Execution states. |
When the value of EDAA32PFR.EL2 is nonzero, this field must be 0b0000.
All other values are reserved.
In an Armv8-A implementation that supports AArch64, this field returns the value of ID_AA64PFR0_EL1.EL2.
Access to this field is RO.
AArch64 EL1 Exception level handling.
The value of this field is an IMPLEMENTATION DEFINED choice of:
EL1 | Meaning |
---|---|
0b0000 | EL1 cannot be executed in AArch64 state. EL1 can be executed in AArch32 state only. |
0b0001 |
EL1 can be executed in AArch64 state only. |
0b0010 |
EL1 can be executed in both Execution states. |
All other values are reserved.
In an Armv8-A implementation that supports AArch64, this field returns the value of ID_AA64PFR0_EL1.EL1.
Access to this field is RO.
AArch64 EL0 Exception level handling.
The value of this field is an IMPLEMENTATION DEFINED choice of:
EL0 | Meaning |
---|---|
0b0000 | EL0 cannot be executed in AArch64 state. EL0 can be executed in AArch32 state only. |
0b0001 |
EL0 can be executed in AArch64 state only. |
0b0010 |
EL0 can be executed in both Execution states. |
All other values are reserved.
In an Armv8-A implementation that supports AArch64, this field returns the value of ID_AA64PFR0_EL1.EL0.
Access to this field is RO.
Component | Offset | Instance |
---|---|---|
Debug | 0xD20 | EDPFR |
This interface is accessible as follows: