Holds the stack pointer associated with EL1. When executing at EL1, the value of SPSel.SP determines the current stack pointer:
SPSel.SP | Current stack pointer |
---|---|
0b0 | SP_EL0 |
0b1 | SP_EL1 |
There are no configuration notes.
SP_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Stack pointer | |||||||||||||||||||||||||||||||
Stack pointer |
Stack pointer.
The reset behavior of this field is:
This accessibility information only applies to accesses using the MRS or MSR instructions.
When the value of SPSel.SP is 1, this register is also accessible at EL1 as the current stack pointer.
When the value of SPSel.SP is 0, SP_EL0 is used as the current stack pointer at all Exception levels.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, SP_EL1
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0100 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X[t, 64] = NVMem[0x240]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then X[t, 64] = SP_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = SP_EL1;
MSR SP_EL1, <Xt>
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0100 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem[0x240] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then SP_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then SP_EL1 = X[t, 64];