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ID_PFR1_EL1: AArch32 Processor Feature Register 1

Purpose

Gives information about the AArch32 programmers' model.

Must be interpreted with ID_PFR0_EL1.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.

Configuration

AArch64 System register ID_PFR1_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_PFR1[31:0].

Attributes

ID_PFR1_EL1 is a 64-bit register.

Field descriptions

When AArch32 is supported:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
GICVirt_fracSec_fracGenTimerVirtualizationMProgModSecurityProgMod

Bits [63:32]

Reserved, RES0.

GIC, bits [31:28]

System register GIC CPU interface.

The value of this field is an IMPLEMENTATION DEFINED choice of:

GICMeaning
0b0000

GIC CPU interface system registers not implemented.

0b0001

System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported.

0b0011

System register interface to version 4.1 of the GIC CPU interface is supported.

All other values are reserved.

Access to this field is RO.

Virt_frac, bits [27:24]

Virtualization fractional field. When the Virtualization field is 0b0000, determines the support for Virtualization Extensions.

The value of this field is an IMPLEMENTATION DEFINED choice of:

Virt_fracMeaning
0b0000

No Virtualization Extensions are implemented.

0b0001

The following Virtualization Extensions are implemented:

  • The SCR.SIF bit, if EL3 is implemented.
  • The modifications to the SCR.AW and SCR.FW bits described in the Virtualization Extensions, if EL3 is implemented.
  • The MSR (banked register) and MRS (banked register) instructions.
  • The ERET instruction.

All other values are reserved.

In Armv8-A, the permitted values are:

This field is valid only when the value of ID_PFR1_EL1.Virtualization is 0, otherwise it holds the value 0b0000.

Note

The ID_ISAR registers do not identify whether the instructions added by the Virtualization Extensions are implemented.

Access to this field is RO.

Sec_frac, bits [23:20]

Security fractional field. When the Security field is 0b0000, determines the support for Security Extensions.

The value of this field is an IMPLEMENTATION DEFINED choice of:

Sec_fracMeaning
0b0000

No Security Extensions are implemented.

0b0001

The following Security Extensions are implemented:

  • The VBAR register.
  • The TTBCR.PD0 and TTBCR.PD1 bits.
0b0010

As for 0b0001, plus the ability to access Secure or Non-secure physical memory is supported.

All other values are reserved.

In Armv8-A, the permitted values are:

This field is valid only when the value of ID_PFR1_EL1.Security is 0, otherwise it holds the value 0b0000.

Access to this field is RO.

GenTimer, bits [19:16]

Generic Timer support.

The value of this field is an IMPLEMENTATION DEFINED choice of:

GenTimerMeaning
0b0000

Generic Timer is not implemented.

0b0001

Generic Timer is implemented.

0b0010

Generic Timer is implemented, and also includes support for CNTHCTL.EVNTIS and CNTKCTL.EVNTIS fields, and CNTPCTSS and CNTVCTSS counter views.

All other values are reserved.

FEAT_ECV implements the functionality identified by the value 0b0010.

In Armv8.0, the only permitted value is 0b0001.

From Armv8.6, the only permitted value is 0b0010.

Access to this field is RO.

Virtualization, bits [15:12]

Virtualization support.

The value of this field is an IMPLEMENTATION DEFINED choice of:

VirtualizationMeaning
0b0000

EL2, Hyp mode, and the HVC instruction not implemented.

0b0001

EL2, Hyp mode, the HVC instruction, and all the features described by Virt_frac == 0b0001 implemented.

All other values are reserved.

In Armv8-A, the permitted values are:

In an implementation that includes EL2, if EL2 cannot use AArch32 but EL1 can use AArch32 then this field has the value 0b0001.

If EL1 cannot use AArch32 then this field has the value 0b0000.

Note

The ID_ISARs do not identify whether the HVC instruction is implemented.

Access to this field is RO.

MProgMod, bits [11:8]

M-profile programmers' model support.

The value of this field is an IMPLEMENTATION DEFINED choice of:

MProgModMeaning
0b0000

Not supported.

0b0010

Support for two-stack programmers' model.

All other values are reserved.

In Armv8-A the only permitted value is 0b0000.

Access to this field is RO.

Security, bits [7:4]

Security support.

The value of this field is an IMPLEMENTATION DEFINED choice of:

SecurityMeaning
0b0000

EL3, Monitor mode, and the SMC instruction not implemented.

0b0001

EL3, Monitor mode, the SMC instruction, and all the features described by Sec_frac == 0b0001 implemented.

0b0010

As for 0b0001, and adds the ability to set the NSACR.RFR bit. Not permitted in Armv8 as the NSACR.RFR bit is RES0.

All other values are reserved.

In Armv8-A, the permitted values are:

In an implementation that includes EL3, if EL3 cannot use AArch32 but EL1 can use AArch32 then this field has the value 0b0001.

If EL1 cannot use AArch32 then this field has the value 0b0000.

Access to this field is RO.

ProgMod, bits [3:0]

Support for the standard programmers' model for Armv4 and later. Model must support User, FIQ, IRQ, Supervisor, Abort, Undefined, and System modes.

The value of this field is an IMPLEMENTATION DEFINED choice of:

ProgModMeaning
0b0000

Not supported.

0b0001

Supported.

All other values are reserved.

In Armv8-A, the permitted values are 0b0001 and 0b0000.

If EL1 cannot use AArch32 then this field has the value 0b0000.

Access to this field is RO.

Otherwise:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
UNKNOWN
UNKNOWN

Bits [63:0]

Reserved, UNKNOWN.

Accessing ID_PFR1_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ID_PFR1_EL1

op0op1CRnCRmop2
0b110b0000b00000b00010b001

if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = ID_PFR1_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = ID_PFR1_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ID_PFR1_EL1;