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NSACR: Non-Secure Access Control Register

Purpose

When EL3 is implemented and can use AArch32, defines the Non-secure access permissions to Trace, Advanced SIMD and floating-point functionality. Also includes IMPLEMENTATION DEFINED bits that can define Non-secure access permissions for IMPLEMENTATION DEFINED functionality.

Configuration

This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to NSACR are UNDEFINED.

Note

In AArch64 state, the NSACR controls are replaced by controls in CPTR_EL3.

Attributes

NSACR is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0NSTRCDISRES0IMPLEMENTATION DEFINEDNSASEDISRES0cp11cp10RES0

If EL3 is implemented and is using AArch64 then:

If EL3 is not implemented, then any read of the NSACR from EL2 or EL1 returns a value of 0x00000C00.

Bits [31:21]

Reserved, RES0.

NSTRCDIS, bit [20]

Disables Non-secure System register accesses to all implemented trace registers.

NSTRCDISMeaning
0b0

This control has no effect on:

  • System register access to implemented trace registers.
  • The behavior of CPACR.TRCDIS and HCPTR.TTA.
0b1

Non-secure System register accesses to all implemented trace registers are disabled, meaning:

  • CPACR.TRCDIS behaves as RAO/WI in Non-secure state, regardless of its actual value.
  • HCPTR.TTA behaves as RAO/WI, regardless of its actual value.

The implementation of this field must correspond to the implementation of the CPACR.TRCDIS field:

Note

System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.

The reset behavior of this field is:

Bit [19]

Reserved, RES0.

IMPLEMENTATION DEFINED, bits [18:16]

IMPLEMENTATION DEFINED.

NSASEDIS, bit [15]

Disables Non-secure access to the Advanced SIMD functionality.

NSASEDISMeaning
0b0

This control has no effect on:

  • Non-secure access to Advanced SIMD functionality.
  • The behavior of CPACR.ASEDIS and HCPTR.TASE.
0b1

Non-secure access to the Advanced SIMD functionality is disabled, meaning:

  • CPACR.ASEDIS behaves as RAO/WI in Non-secure state, regardless of its actual value.
  • HCPTR.TASE behaves as RAO/WI, regardless of its actual value.

The implementation of this field must correspond to the implementation of the CPACR.ASEDIS field:

The reset behavior of this field is:

Bits [14:12]

Reserved, RES0.

cp11, bit [11]

The value of this field is ignored. If this field is programmed with a different value to the cp10 field then this field is UNKNOWN on a direct read of the NSACR.

If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES0.

The reset behavior of this field is:

cp10, bit [10]

Enable Non-secure access to the Advanced SIMD and floating-point features. Possible values of the fields are:

cp10Meaning
0b0

Advanced SIMD and floating-point features can be accessed only from Secure state. Any attempt to access this functionality from Non-secure state is UNDEFINED.

When the PE is in Non-secure state:

  • The CPACR.{cp11, cp10} fields ignore writes and read as 0b00, access denied.
  • The HCPTR.{TCP11, TCP10} fields behave as RAO/WI, regardless of their actual values.
0b1

Advanced SIMD and floating-point features can be accessed from both Security states.

If Non-secure access to the Advanced SIMD and floating-point functionality is enabled, the CPACR must be checked to determine the level of access that is permitted.

The Advanced SIMD and floating-point features controlled by these fields are:

If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES0.

The reset behavior of this field is:

Bits [9:0]

Reserved, RES0.

Accessing NSACR

Accesses to this register use the following encodings in the System register encoding space:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11110b0000b00010b00010b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T1 == '1' then AArch32.TakeHypTrapException(0x03); elsif !ELUsingAArch32(EL2) && SCR_EL3.<NS,EEL2> == '01' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif !HaveEL(EL3) || (!ELUsingAArch32(EL3) && SCR_EL3.NS == '1') then R[t] = Zeros(20):'1100':Zeros(8); else R[t] = NSACR; elsif PSTATE.EL == EL2 then if !HaveEL(EL3) || (!ELUsingAArch32(EL3) && SCR_EL3.NS == '1') then R[t] = Zeros(20):'1100':Zeros(8); else R[t] = NSACR; elsif PSTATE.EL == EL3 then R[t] = NSACR;

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11110b0000b00010b00010b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T1 == '1' then AArch32.TakeHypTrapException(0x03); elsif !ELUsingAArch32(EL2) && SCR_EL3.<NS,EEL2> == '01' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if CP15SDISABLE2 == Signal_High then UNDEFINED; else NSACR = R[t];