← HomePMEVFILT2R<n>, n = 0 - 63
Performance Monitors Event Filter Registers
Provides additional IMPLEMENTATION DEFINED configuration controls for PMU counters.
Each PMEVFILT2R<n> register can provide additional configuration controls for a PMU counter, where:
- For values of n less than 31, if event counter n is implemented, then the controls are for PMU event counter <n>.
- For n equal to 31, the controls are for the cycle counter, PMCCNTR_EL0;
- For n equal to 32, if FEAT_PMUv3_ICNTR is implemented, the controls are for the instruction counter, PMICNTR_EL0;
- For all other values of n, PMEVFILT2R<n> is not implemented.
Although this mapping is recommended, it is not required and the function of each register is IMPLEMENTATION DEFINED.
Configuration
This register is present only when FEAT_PMUv3_EXT is implemented, FEAT_PMUv3 is implemented, and an implementation implements PMEVFILT2R<n>. Otherwise, direct accesses to PMEVFILT2R<n> are RES0.
PMEVFILT2R<n> is in the Core power domain.
If PMEVFILT2R<n> is not implemented:
- When IsCorePowered() && !DoubleLockStatus() && !OSLockStatus() && AllowExternalPMUAccess(), accesses are RES0.
- Otherwise, it is CONSTRAINED UNPREDICTABLE whether accesses to this register are RES0 or generate an error response.
Attributes
PMEVFILT2R<n> is a:
- 64-bit register when FEAT_PMUv3_EXT64 is implemented
- 32-bit register otherwise
This register is part of the PMU block.
Field descriptions
When FEAT_PMUv3_EXT64 is implemented:
IMPLEMENTATION DEFINED, bits [63:0]:
Otherwise:
IMPLEMENTATION DEFINED, bits [31:0]:
Access Instructions
Accesses to this register use the following encodings:
When FEAT_PMUv3_EXT32 is implemented:
[31:0] Accessible at offset 0x800 + (4 * n) from PMU
- When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc), accesses to this register generate an error response.
- When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus(), accesses to this register generate an error response.
- When FEAT_PMUv3_EXTPMN is implemented, IsRange3Counter(n), and !IsMostSecureAccess(addrdesc), accesses to this register are RAZ/WI.
- When SoftwareLockStatus(addrdesc), accesses to this register are RO.
- Otherwise, accesses to this register are RW.
()
When FEAT_PMUv3_EXT64 is implemented:
[63:0] Accessible at offset 0x800 + (8 * n) from PMU
- When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc), accesses to this register generate an error response.
- When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus(), accesses to this register generate an error response.
- When FEAT_PMUv3_EXTPMN is implemented, IsRange3Counter(n), and !IsMostSecureAccess(addrdesc), accesses to this register are RAZ/WI.
- Otherwise, accesses to this register are RW.
()
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