Performance Monitors Device Type register
Indicates to a debugger that this component is part of a PE's performance monitor interface.
This register is present only when FEAT_PMUv3_EXT is implemented and FEAT_PMU_PIDR is implemented. Otherwise, direct accesses to PMDEVTYPE are RES0.
If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.
PMDEVTYPE is a 32-bit register.
This register is part of the PMU block.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | SUB | MAJOR | |||||||||||||||||||||||||||||
Reserved, RES0.
Subtype. Indicates this is a component within a PE.
Reads as 0b0001.
Access to this field is RO.
Major type.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| MAJOR | Meaning |
|---|---|
| 0b0000 |
Unspecified. |
| 0b0110 |
Performance monitor component. |
FEAT_PMUv3 implements the functionality described by the value 0b0110.
Access to this field is RO.
Accesses to this register use the following encodings:
Accessible at offset 0xFCC from PMU
()
Version 2026.06 — Copyright © 2010-2026 Arm Limited or its affiliates.
This site is provided as a community resource and is NOT affiliated with nor endorsed by Arm Limited.