Encodes the number of counters accessible.
This register is present only when FEAT_PMUv3_ICNTR is implemented. Otherwise, direct accesses to PMCGCR0 are RES0.
PMCGCR0 is in the Core power domain.
PMCGCR0 is a:
This register is part of the PMU block.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | CG1NC | CG0NC | |||||||||||||||||||||||||||||
Reserved, RES0.
Number of counters in group 1, which comprises the instruction counter PMICNTR_EL0.
| CG1NC | Meaning |
|---|---|
| 0x01 |
PMICNTR_EL0 implemented |
Other values are reserved.
Access to this field is RO.
Number of counters in group 0, which comprises the event counters PMEVCNTR<n>_EL0 and the cycle counter PMCCNTR_EL0.
When FEAT_PMUv3_EXTPMN is implemented and the external access to this register is not a Most secure access, this field reads as the Effective value of PMCCR.EPMN plus one.
Otherwise, this field reads as the number of event counters implemented plus one.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | CG1NC | CG0NC | |||||||||||||||||||||||||||||
Reserved, RES0.
Number of counters in group 1, which comprises the instruction counter PMICNTR_EL0.
| CG1NC | Meaning |
|---|---|
| 0x01 |
PMICNTR_EL0 implemented |
Other values are reserved.
Access to this field is RO.
Number of counters in group 0, which comprises the event counters PMEVCNTR<n>_EL0 and the cycle counter PMCCNTR_EL0.
When FEAT_PMUv3_EXTPMN is implemented and the external access to this register is not a Most secure access, this field reads as the Effective value of PMCCR.EPMN plus one.
Otherwise, this field reads as the number of event counters implemented plus one.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Accesses to this register use the following encodings:
[31:0] Accessible at offset 0xCE0 from PMU
[63:0] Accessible at offset 0xCE0 from PMU