← HomePMCCNTR_EL0: Performance Monitors Cycle Counter
Purpose
Holds the value of the processor Cycle Counter, CCNT, that counts processor clock cycles. For more information, see 'Time as measured by the Performance Monitors cycle counter'.
PMCCFILTR_EL0 determines the modes and states in which the PMCCNTR_EL0 can increment.
Configuration
External register PMCCNTR_EL0 bits [63:0] are architecturally mapped to AArch64 System register PMCCNTR_EL0[63:0].
External register PMCCNTR_EL0 bits [63:0] are architecturally mapped to AArch32 System register PMCCNTR[63:0].
This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMCCNTR_EL0 are RES0.
PMCCNTR_EL0 is in the Core power domain.
Attributes
PMCCNTR_EL0 is a 64-bit register.
This register is part of the PMU block.
Field descriptions
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CCNT |
| CCNT |
CCNT, bits [63:0]
Cycle count. Depending on the values of PMCR_EL0.{LC,D}, the cycle count increments in one of the following ways:
- Every processor clock cycle.
- Every 64th processor clock cycle.
Writing 1 to PMCR_EL0.C sets this field to 0.
The reset behavior of this field is:
- On a Cold reset, when FEAT_PMUv3_EXTPMN is implemented,
this field resets
to an architecturally UNKNOWN value.
- On a Warm reset, when FEAT_PMUv3_EXTPMN is not implemented,
this field resets
to an architecturally UNKNOWN value.
Accessing PMCCNTR_EL0
SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
Accesses to this register use the following encodings:
When FEAT_PMUv3_EXT64 is implemented
[63:0] Accessible at offset 0x0F8 from PMU
- When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(), accesses to this register generate an error response.
- When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(), or PMCCR.OSLO == 0) and OSLockStatus(), accesses to this register generate an error response.
- Otherwise, accesses to this register are RW.
When FEAT_PMUv3_EXT32 is implemented
[31:0] Accessible at offset 0x0F8 from PMU
- When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(), accesses to this register generate an error response.
- When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(), or PMCCR.OSLO == 0) and OSLockStatus(), accesses to this register generate an error response.
- When SoftwareLockStatus(), accesses to this register are RO.
- Otherwise, accesses to this register are RW.
When FEAT_PMUv3_EXT32 is implemented
[63:32] Accessible at offset 0x0FC from PMU
- When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(), accesses to this register generate an error response.
- When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(), or PMCCR.OSLO == 0) and OSLockStatus(), accesses to this register generate an error response.
- When SoftwareLockStatus(), accesses to this register are RO.
- Otherwise, accesses to this register are RW.