Trace Status Register
Returns the trace unit status.
External register TRCSTATR bits [31:0] are architecturally mapped to AArch64 System register TRCSTATR[31:0].
This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCSTATR are RES0.
TRCSTATR is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | PMSTABLE | IDLE | |||||||||||||||||||||||||||||
Reserved, RES0.
Programmers' model stable.
| PMSTABLE | Meaning |
|---|---|
| 0b0 |
The programmers' model is not stable. |
| 0b1 |
The programmers' model is stable. |
Accessing this field has the following behavior:
Idle status.
| IDLE | Meaning |
|---|---|
| 0b0 |
The trace unit is not idle. |
| 0b1 |
The trace unit is idle. |
| Component | Offset | Instance |
|---|---|---|
| ETE | 0x00C | TRCSTATR |
Accessible as follows:
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