← Home

TRCSTATR

Trace Status Register

Returns the trace unit status.

Configuration

External register TRCSTATR bits [31:0] are architecturally mapped to AArch64 System register TRCSTATR[31:0].

This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCSTATR are RES0.

Attributes

TRCSTATR is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0PMSTABLEIDLE

Bits [31:2]:

Reserved, RES0.

PMSTABLE, bit [1]:

Programmers' model stable.

PMSTABLEMeaning
0b0

The programmers' model is not stable.

0b1

The programmers' model is stable.

Accessing this field has the following behavior:

IDLE, bit [0]:

Idle status.

IDLEMeaning
0b0

The trace unit is not idle.

0b1

The trace unit is idle.

Accessing TRCSTATR

TRCSTATR can be accessed through the external debug interface:

ComponentOffsetInstance
ETE0x00CTRCSTATR

Accessible as follows:


Version 2025.09 — Copyright © 2010-2025 Arm Limited or its affiliates.

This site is provided as a community resource and is NOT affiliated with nor endorsed by Arm Limited.