TRCCNTRLDVR<n>, n = 0 - 3

Trace Counter Reload Value Register <n>

This sets or returns the reload count value for Counter <n>.

External register TRCCNTRLDVR<n> bits [31:0] are architecturally mapped to AArch64 System register TRCCNTRLDVR<n>[31:0].

This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCCNTRLDVR<n> are RES0.

TRCCNTRLDVR<n> is a 32-bit register.

Field descriptions

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																VALUE

Reserved, RES0.

Contains the reload value for Counter <n>. When a reload event occurs for Counter <n> then the trace unit copies the VALUE<n> field into Counter <n>.

The reset behavior of this field is:

Must be programmed if TRCRSCTLR<a>.GROUP == 0b0010 and TRCRSCTLR<a>.COUNTERS[n] == 1.

If the trace unit is not in the Idle state it is CONSTRAINED UNPREDICTABLE whether writes to this register are ignored.

Component	Offset	Instance
ETE	0x140 + (4 * n)	TRCCNTRLDVR<n>

Accessible as follows:

When OSLockStatus(), or !AllowExternalTraceAccess(addrdesc), or !IsTraceCorePowered(), accesses to this register generate an error response.
When n >= NUM_TRACE_COUNTERS, accesses to this register are RES0.
Otherwise, accesses to this register are RW.

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