Trace Buffer Memory Attribute Register
Controls Trace Buffer Unit accesses to memory.
External register TRBMAR_EL1 bits [63:0] are architecturally mapped to AArch64 System register TRBMAR_EL1[63:0].
TRBMAR_EL1 is in the Core power domain.
This register is present only when FEAT_TRBE_EXT is implemented. Otherwise, direct accesses to TRBMAR_EL1 are RES0.
TRBMAR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | PAS | SH | Attr | ||||||||||||||||||||||||||||
Reserved, RES0.
Physical address specifier. Defines the PAS attribute for memory addressed by the buffer in External mode.
| PAS | Meaning | Applies when |
|---|---|---|
| 0b00 |
Secure. | When FEAT_Secure is implemented |
| 0b01 |
Non-secure. | |
| 0b10 |
Root. | When FEAT_RME is implemented |
| 0b11 |
Realm. | When FEAT_RME is implemented |
All other values are reserved.
If the Trace Buffer Unit is using external mode and either TRBMAR_EL1.PAS is set to a reserved value, or the IMPLEMENTATION DEFINED authentication interface prohibits invasive debug of the Security state corresponding to the physical address space selected by TRBMAR_EL1.PAS, then when the Trace Buffer Unit receives trace data from the trace unit, it does not write the trace data to memory and generates a trace buffer management event. That is, if any of the following apply:
This field is ignored by the PE when SelfHostedTraceEnabled() == TRUE.
The reset behavior of this field is:
Trace buffer stage 1 shareability domain. Defines the shareability domain for Normal memory used by the trace buffer.
| SH | Meaning |
|---|---|
| 0b00 |
Non-shareable. |
| 0b10 |
Outer Shareable. |
| 0b11 |
Inner Shareable. |
All other values are reserved.
If the trace buffer pointers specify virtual addresses, the memory attributes are defined by the translation tables and this field is ignored.
This field is ignored when TRBMAR_EL1.Attr specifies any of the following memory types:
All Device and Normal Inner Non-cacheable Outer Non-cacheable memory regions are always treated as Outer Shareable.
The reset behavior of this field is:
Trace buffer stage 1 memory type and attributes. Defines the memory type and, for Normal memory, the cacheability attributes, for memory addressed by the trace buffer.
The encoding of this field is the same as that of a MAIR_ELx.Attr<n> field, as follows:
| Attr | Meaning | |
|---|---|---|
| '0000dd00' | Device memory. See encoding of 'dd' for the type of Device memory. | |
| '0000dd01' | If FEAT_XS is implemented: Device memory with the XS attribute set to 0. See encoding of 'dd' for the type of Device memory. Otherwise,UNPREDICTABLE. | |
| '0000dd1x' | UNPREDICTABLE. | |
| 'ooooiiii' | where oooo != 0000 and iiii != 0000 | Normal memory. See encoding of 'oooo' and 'iiii' for the type of Normal memory. |
| '01000000' | If FEAT_XS is implemented: Normal Inner Non-cacheable, Outer Non-cacheable memory with the XS attribute set to 0. Otherwise,UNPREDICTABLE. | |
| '10100000' | If FEAT_XS is implemented: Normal Inner Write-through Cacheable, Outer Write-through Cacheable, Read-Allocate, No-Write Allocate, Non-transient memory with the XS attribute set to 0. Otherwise,UNPREDICTABLE. | |
| '11110000' | If FEAT_MTE2 is implemented: Tagged Normal Inner Write-Back, Outer Write-Back, Read-Allocate, Write-Allocate Non-transient memory. Otherwise,UNPREDICTABLE. | |
| 'xxxx0000' | where xxxx != 0000 and xxxx != 0100 and xxxx != 1010 and xxxx != 1111 | UNPREDICTABLE. |
dd is encoded as follows:
| 'dd' | Meaning |
|---|---|
| '00' | Device-nGnRnE memory. |
| '01' | Device-nGnRE memory. |
| '10' | Device-nGRE memory. |
| '11' | Device-GRE memory. |
oooo is encoded as follows:
| 'oooo' | Meaning | |
|---|---|---|
| '0000' | See encoding of Attr. | |
| '00RW' | where RW != 00 | Normal memory, Outer Write-Through Transient. |
| '0100' | Normal memory, Outer Non-cacheable. | |
| '01RW' | where RW != 00 | Normal memory, Outer Write-Back Transient. |
| '10RW' | Normal memory, Outer Write-Through Non-transient. | |
| '11RW' | Normal memory, Outer Write-Back Non-transient. |
R encodes the Outer Read-Allocate policy and W encodes the Outer Write-Allocate policy.
iiii is encoded as follows:
| 'iiii' | Meaning | |
|---|---|---|
| '0000' | See encoding of Attr. | |
| '00RW' | where RW != 00 | Normal memory, Inner Write-Through Transient. |
| '0100' | Normal memory, Inner Non-cacheable. | |
| '01RW' | where RW != 00 | Normal memory, Inner Write-Back Transient. |
| '10RW' | Normal memory, Inner Write-Through Non-transient. | |
| '11RW' | Normal memory, Inner Write-Back Non-transient. |
R encodes the Inner Read-Allocate policy and W encodes the Inner Write-Allocate policy.
In oooo and iiii, R and W are encoded as follows:
| 'R' or 'W' | Meaning |
|---|---|
| '0' | No Allocate. |
| '1' | Allocate. |
When FEAT_XS is implemented, stage 1 Inner Write-Back Cacheable, Outer Write-Back Cacheable memory types have the XS attribute set to 0.
If the trace buffer pointers specify virtual addresses, the memory attributes are defined by the translation tables and this field is ignored.
The reset behavior of this field is:
The PE might ignore a write to TRBMAR_EL1 if any of the following apply:
| Component | Offset | Instance |
|---|---|---|
| TRBE | 0x028 | TRBMAR_EL1 |
Accessible as follows:
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