TRBDEVID1

Device Configuration Register 1

Provides discovery information for the component.

For additional information, see the CoreSight Architecture Specification.

TRBDEVID1 is in the Core power domain.

This register is present only when FEAT_TRBE_EXT is implemented. Otherwise, direct accesses to TRBDEVID1 are RES0.

TRBDEVID1 is a 32-bit register.

Field descriptions

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0								PMG_MAX								PARTID_MAX

Reserved, RES0.

Largest permitted PMG value. The TRBMPAM_EL1.PMG field must implement at least enough bits to represent TRBDEVID1.PMG_MAX.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Reserved, RES0.

Largest permitted PARTID value. The TRBMPAM_EL1.PARTID field must implement at least enough bits to represent TRBDEVID1.PARTID_MAX.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Reserved, RES0.

Component	Offset	Instance
TRBE	0xFC4	TRBDEVID1

Accessible as follows:

When DoubleLockStatus() or !IsCorePowered(), accesses to this register generate an error response.
Otherwise, accesses to this register are RO.

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