Interrupt Controller Type Register 2
Provides information about which features the GIC implementation supports.
When GICD_CTLR.DS == 0, this register is Common.
GICD_TYPER2 is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | nASSGIcap | VIL | RES0 | VID | |||||||||||||||||||||||||||
Reserved, RES0.
Indicates whether SGIs can be configured to not have an active state.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| nASSGIcap | Meaning |
|---|---|
| 0b0 |
SGIs have an active state. |
| 0b1 |
SGIs can be globally configured not to have an active state. |
This bit is RES0 on implementations that support two Security states.
Access to this field is RO.
Indicates whether 16 bits of vPEID are implemented.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| VIL | Meaning |
|---|---|
| 0b0 |
GIC supports 16-bit vPEID. |
| 0b1 |
GIC supports GICD_TYPER2.VID + 1 bits of vPEID. |
Access to this field is RO.
Reserved, RES0.
Reserved, RES0.
The number of bits vPEID.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| VID | Meaning |
|---|---|
| 0b00000..0b01111 |
The number of vPEID bits implemented, minus one. |
Access to this field is RO.
Reserved, RES0.
| Component | Frame | Offset | Instance |
|---|---|---|---|
| GIC Distributor | Dist_base | 0x000C | GICD_TYPER2 |
Accesses to this register are RO.
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