GICD_SETSPI_SR

Set Secure SPI Pending Register

Adds the pending state to a valid SPI.

A write to this register changes the state of an inactive SPI to pending, and the state of an active SPI to active and pending.

If GICD_TYPER.MBIS == 0, this register is reserved.

When GICD_CTLR.DS == 1, this register is WI.

GICD_SETSPI_SR is a 32-bit register.

Field descriptions

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																			INTID

Reserved, RES0.

The INTID of the SPI.

The function of this register depends on whether the targeted SPI is configured to be an edge-triggered or level-sensitive interrupt:

For an edge-triggered interrupt, a write to GICD_SETSPI_NSR or GICD_SETSPI_SR adds the pending state to the targeted interrupt. It will stop being pending on activation, or if the pending state is removed by a write to GICD_CLRSPI_NSR, GICD_CLRSPI_SR, or GICD_ICPENDR<n>.
For a level-sensitive interrupt, a write to GICD_SETSPI_NSR or GICD_SETSPI_SR adds the pending state to the targeted interrupt. It will remain pending until it is deasserted by a write to GICD_CLRSPI_NSR or GICD_CLRSPI_SR. If the interrupt is activated between having the pending state added and being deactivated, then the interrupt will be active and pending.

Writes to this register have no effect if:

16-bit accesses to bits [15:0] of this register must be supported.

Component	Frame	Offset	Instance
GIC Distributor	Dist_base	0x0050	GICD_SETSPI_SR

Accessible as follows:

When GICD_CTLR.DS == 1, accesses to this register are WI.
When GICD_CTLR.DS == 0 and an access is Secure, accesses to this register are WO.
When GICD_CTLR.DS == 0 and an access is Non-secure, accesses to this register are WI.
When GICD_CTLR.DS == 0, FEAT_RME is implemented, and an access is Root, accesses to this register are WO.
When GICD_CTLR.DS == 0, FEAT_RME is implemented, and an access is Realm, accesses to this register are WI.

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