Activity Monitors Root Control Register
Control register for Root, Realm, Secure, and Non-secure access to External AMU registers.
It is IMPLEMENTATION DEFINED whether AMROOTCR is implemented in the Core power domain or in the Debug power domain.
This register is present only when FEAT_AMU_EXTACR is implemented and FEAT_RME is implemented. Otherwise, direct accesses to AMROOTCR are RES0.
AMROOTCR is a 64-bit register.
This register is part of the AMU block.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| IMPL | RES0 | RA | RES0 | ||||||||||||||||||||||||||||
Reserved, RES0.
| IMPL | Meaning |
|---|---|
| 0b1 |
Indicates AMROOTCR is present. |
Access to this field is RAO/WI.
Reserved, RES0.
Register Access to all External Activity Monitors registers.
| RA | Meaning |
|---|---|
| 0b000 |
Root register access is enabled. Access from other address spaces is disabled, meaning accesses to all External AMU registers are RAZ/WI. |
| 0b001 |
Root and Realm register access is enabled. Access from other address spaces is disabled, meaning accesses to all External AMU registers are RAZ/WI. |
| 0b010 |
Root and Secure register access is enabled. Access from other address spaces is disabled, meaning accesses to all External AMU registers are RAZ/WI. |
| 0b011 |
Root, Secure, Non-secure and Realm register access is enabled. |
Other values are reserved.
For the CoreSight management registers, 0xFA8 to 0xFFC, it is IMPLEMENTATION DEFINED whether these registers are RO or RAZ/WI when register access is disabled by this field.
Reserved, RES0.
Accesses to this register use the following encodings:
Accessible at offset 0xE48 from AMU
()
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