Activity Monitors Event Counter Registers 0
Provides access to the architected activity monitor event counters.
External register AMEVCNTR0<n> bits [63:0] are architecturally mapped to AArch64 System register AMEVCNTR0<n>_EL0[63:0].
External register AMEVCNTR0<n> bits [31:0] are architecturally mapped to AArch32 System register AMEVCNTR0<n>[31:0].
It is IMPLEMENTATION DEFINED whether AMEVCNTR0<n> is implemented in the Core power domain or in the Debug power domain.
This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMEVCNTR0<n> are RES0.
AMEVCNTR0<n> is a 64-bit register.
This register is part of the AMU block.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACNT | |||||||||||||||||||||||||||||||
| ACNT | |||||||||||||||||||||||||||||||
Architected activity monitor event counter n.
Value of architected activity monitor event counter n, where n is the number of this register and is a number from 0 to 3.
The reset behavior of this field is:
If <n> is greater than or equal to the number of architected activity monitor event counters, reads of AMEVCNTR0<n> are RAZ. Software must treat reserved accesses as RES0. See 'Access requirements for reserved and unallocated registers'.
AMCGCR.CG0NC identifies the number of architected activity monitor event counters.
Accesses to this register use the following encodings:
[63:0] Accessible at offset 0x000 + (8 * n) from AMU
()
[63:0] Accessible at offset 0x000 + (8 * n) from AMU
()
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