← HomeAMDEVARCH: Activity Monitors Device Architecture Register
Purpose
Identifies the programmers' model architecture of the AMU component.
Configuration
It is IMPLEMENTATION DEFINED whether AMDEVARCH is implemented in the Core power domain or in the Debug power domain.
This register is present only when FEAT_AMUv1 is implemented and an implementation implements AMDEVARCH. Otherwise, direct accesses to AMDEVARCH are RES0.
Attributes
AMDEVARCH is a 32-bit register.
This register is part of the AMU block.
Field descriptions
ARCHITECT, bits [31:21]
Defines the architect of the component. For Activity Monitors, this is Arm Limited.
Bits [31:28] are the JEP106 continuation code, 0b0100.
Bits [27:21] are the JEP106 identification code, 0b0111011.
Reads as 0b01000111011.
Access to this field is RO.
PRESENT, bit [20]
DEVARCH present. Indicates that the AMDEVARCH register is present.
Reads as 0b1.
Access to this field is RO.
REVISION, bits [19:16]
Defines the architecture revision. For architectures defined by Arm this is the minor revision.
| REVISION | Meaning |
|---|
| 0b0000 |
Architecture revision is AMUv1.
|
All other values are reserved.
Access to this field is RO.
ARCHID, bits [15:0]
Defines this part to be an AMU component. For architectures defined by Arm this is further subdivided.
For AMU:
- Bits [15:12] are the architecture version, also identified as AMDEVARCH.ARCHVER.
- Bits [11:0] are the architecture part number, also identified as AMDEVARCH.ARCHPART.
AMDEVARCH.ARCHVER = 0x0, which corresponds to AMU architecture version AMUv1.
If FEAT_AMU_EXT32 is implemented, AMDEVARCH is 0xA66.
If FEAT_AMU_EXT64 is implemented, AMDEVARCH is 0xA67.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| ARCHID | Meaning |
|---|
| 0x0A66 |
AMUv1, with FEAT_AMU_EXT32 implemented.
|
| 0x0A67 |
AMUv1, with FEAT_AMU_EXT64 implemented.
|
Access to this field is RO.
Accessing AMDEVARCH
Accesses to this register use the following encodings:
When FEAT_AMU_EXT64 is implemented
Accessible at offset 0xFBC from AMU
- When boolean IMPLEMENTATION_DEFINED "AMU CoreSight management registers ignore access controls", accesses to this register are RO.
- When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR.RA IN {0b01, 0b00}, accesses to this register are RAZ/WI.
- When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR.RA IN {0b10, 0b00}, accesses to this register are RAZ/WI.
- When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR.RA != 0b11, accesses to this register are RAZ/WI.
- When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR.NSRA == 0, accesses to this register are RAZ/WI.
- Otherwise, accesses to this register are RO.
When FEAT_AMU_EXT32 is implemented
Accessible at offset 0xFBC from AMU
- When boolean IMPLEMENTATION_DEFINED "AMU CoreSight management registers ignore access controls", accesses to this register are RO.
- When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR.RA IN {0b01, 0b00}, accesses to this register are RAZ/WI.
- When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR.RA IN {0b10, 0b00}, accesses to this register are RAZ/WI.
- When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR.RA != 0b11, accesses to this register are RAZ/WI.
- When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR.NSRA == 0, accesses to this register are RAZ/WI.
- Otherwise, accesses to this register are RO.