← HomeAMCIDR3: Activity Monitors Component Identification Register 3
Purpose
Provides information to identify an activity monitors component.
For more information, see 'About the Component identification scheme'.
Configuration
It is IMPLEMENTATION DEFINED whether AMCIDR3 is implemented in the Core power domain or in the Debug power domain.
This register is present only when FEAT_AMUv1 is implemented and an implementation implements AMCIDR3. Otherwise, direct accesses to AMCIDR3 are RES0.
Attributes
AMCIDR3 is a 32-bit register.
This register is part of the AMU block.
Field descriptions
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | PRMBL_3 |
Bits [31:8]
PRMBL_3, bits [7:0]
Preamble.
Reads as 0xB1.
Access to this field is RO.
Accessing AMCIDR3
Accesses to this register use the following encodings:
Accessible at offset 0xFFC from AMU
- When boolean IMPLEMENTATION_DEFINED "AMU CoreSight management registers ignore access controls", accesses to this register are RO.
- When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR.RA IN {0b01, 0b00}, accesses to this register are RAZ/WI.
- When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR.RA IN {0b10, 0b00}, accesses to this register are RAZ/WI.
- When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR.RA != 0b11, accesses to this register are RAZ/WI.
- When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR.NSRA == 0, accesses to this register are RAZ/WI.
- Otherwise, accesses to this register are RO.