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VBAR_EL2

Vector Base Address Register (EL2)

Holds the vector base address for any exception that is taken to EL2.

Configuration

AArch64 System register VBAR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HVBAR[31:0].

This register is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to VBAR_EL2 are UNDEFINED.

If EL2 is not implemented, this register is RES0 from EL3.

This register has no effect if EL2 is not enabled in the current Security state.

Attributes

VBAR_EL2 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
VBA
VBARES0

VBA, bits [63:11]:

Vector Base Address. Base address of the exception vectors for exceptions taken to EL2.

If FEAT_LVA3 is implemented:

Otherwise :

If FEAT_LVA is implemented:

If FEAT_LVA is not implemented:

The reset behavior of this field is:

Bits [10:0]:

Reserved, RES0.

Access Instructions

When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name VBAR_EL2 or VBAR_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, VBAR_EL2

(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b0000, op2 = 0b000)

if !IsFeatureImplemented(FEAT_AA64) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then X[t, 64] = VBAR_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = VBAR_EL2;

MSR VBAR_EL2, <Xt>

(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b0000, op2 = 0b000)

if !IsFeatureImplemented(FEAT_AA64) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then VBAR_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then VBAR_EL2 = X[t, 64];

When FEAT_VHE is implemented:

MRS <Xt>, VBAR_EL1

(op0 = 0b11, op1 = 0b000, CRn = 0b1100, CRm = 0b0000, op2 = 0b000)

if !IsFeatureImplemented(FEAT_AA64) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '011' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.VBAR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X[t, 64] = NVMem[0x250]; else X[t, 64] = VBAR_EL1; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then X[t, 64] = VBAR_EL2; else X[t, 64] = VBAR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = VBAR_EL1;

When FEAT_VHE is implemented:

MSR VBAR_EL1, <Xt>

(op0 = 0b11, op1 = 0b000, CRn = 0b1100, CRm = 0b0000, op2 = 0b000)

if !IsFeatureImplemented(FEAT_AA64) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '011' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.VBAR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem[0x250] = X[t, 64]; else VBAR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then VBAR_EL2 = X[t, 64]; else VBAR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then VBAR_EL1 = X[t, 64];


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