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UAO

User Access Override

Allows access to the User Access Override bit.

Configuration

This register is present only when FEAT_UAO is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to UAO are UNDEFINED.

This register is a Special-purpose register.

Attributes

UAO is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0UAORES0

Bits [63:24]:

Reserved, RES0.

UAO, bit [23]:

User Access Override.

UAOMeaning
0b0

Explicit Memory Effects generated by unprivileged memory access instructions and described as unprivileged are unprivileged.

0b1

Explicit Memory Effects generated by unprivileged memory access instructions and described as unprivileged are privileged.

The Effective value of PSTATE.UAO is 0 when execution is at EL0.

The Effective value of PSTATE.UAO is 1 when any of the following is true:

Bits [22:0]:

Reserved, RES0.

Access Instructions

For more information about the operation of the MSR (immediate) accessor, see 'MSR (immediate)'.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, UAO

(op0 = 0b11, op1 = 0b000, CRn = 0b0100, CRm = 0b0010, op2 = 0b100)

if !(IsFeatureImplemented(FEAT_UAO) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then X{64}(t) = Zeros{40} :: PSTATE.UAO :: Zeros{23}; elsif PSTATE.EL == EL2 then X{64}(t) = Zeros{40} :: PSTATE.UAO :: Zeros{23}; elsif PSTATE.EL == EL3 then X{64}(t) = Zeros{40} :: PSTATE.UAO :: Zeros{23}; end;

MSR UAO, <Xt>

(op0 = 0b11, op1 = 0b000, CRn = 0b0100, CRm = 0b0010, op2 = 0b100)

if !(IsFeatureImplemented(FEAT_UAO) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then PSTATE.UAO = X{64}(t)[23]; elsif PSTATE.EL == EL2 then PSTATE.UAO = X{64}(t)[23]; elsif PSTATE.EL == EL3 then PSTATE.UAO = X{64}(t)[23]; end;

MSR UAO, #<imm>

(op0 = 0b00, op1 = 0b000, CRn = 0b0100, op2 = 0b011)


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