Trace ViewInst Start/Stop PE Comparator Control Register
Use this to select, or read, which PE Comparator Inputs can control the ViewInst start/stop function.
AArch64 System register TRCVIPCSSCTLR bits [31:0] are architecturally mapped to External register TRCVIPCSSCTLR[31:0].
This register is present only when FEAT_ETE is implemented, System register access to the trace unit registers is implemented, and UInt(TRCIDR4.NUMPC) > 0. Otherwise, direct accesses to TRCVIPCSSCTLR are UNDEFINED.
TRCVIPCSSCTLR is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | STOP[7] | STOP[6] | STOP[5] | STOP[4] | STOP[3] | STOP[2] | STOP[1] | STOP[0] | RES0 | START[7] | START[6] | START[5] | START[4] | START[3] | START[2] | START[1] | START[0] | ||||||||||||||
Reserved, RES0.
Selects whether PE Comparator Input <m> is in use with the ViewInst start/stop function for the purpose of stopping trace.
| STOP[<m>] | Meaning |
|---|---|
| 0b0 |
The PE Comparator Input <m> is not selected as a stop resource. |
| 0b1 |
The PE Comparator Input <m> is selected as a stop resource. |
The reset behavior of this field is:
Accessing this field has the following behavior:
Reserved, RES0.
Selects whether PE Comparator Input <m> is in use with the ViewInst start/stop function for the purpose of starting trace.
| START[<m>] | Meaning |
|---|---|
| 0b0 |
The PE Comparator Input <m> is not selected as a start resource. |
| 0b1 |
The PE Comparator Input <m> is selected as a start resource. |
The reset behavior of this field is:
Accessing this field has the following behavior:
Must be programmed if TRCIDR4.NUMPC != 0b0000.
If the trace unit is not in the Idle state it is CONSTRAINED UNPREDICTABLE whether writes to this register are ignored.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, TRCVIPCSSCTLR
(op0 = 0b10, op1 = 0b001, CRn = 0b0000, CRm = 0b0011, op2 = 0b010)
if !(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && UInt(TRCIDR4().NUMPC) > 0) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if CPACR_EL1().TTA == '1' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().TRC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCVIPCSSCTLR(); end; elsif PSTATE.EL == EL2 then if CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCVIPCSSCTLR(); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TTA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCVIPCSSCTLR(); end; end;
MSR TRCVIPCSSCTLR, <Xt>
(op0 = 0b10, op1 = 0b001, CRn = 0b0000, CRm = 0b0011, op2 = 0b010)
if !(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR) && UInt(TRCIDR4().NUMPC) > 0) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if CPACR_EL1().TTA == '1' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().TRC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCVIPCSSCTLR() = X{64}(t); end; elsif PSTATE.EL == EL2 then if CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCVIPCSSCTLR() = X{64}(t); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TTA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCVIPCSSCTLR() = X{64}(t); end; end;
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