Trace ID Register 8
Returns the maximum speculation depth of the instruction trace element stream.
AArch64 System register TRCIDR8 bits [31:0] are architecturally mapped to External register TRCIDR8[31:0].
This register is present only when FEAT_ETE is implemented and System register access to the trace unit registers is implemented. Otherwise, direct accesses to TRCIDR8 are UNDEFINED.
TRCIDR8 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| MAXSPEC | |||||||||||||||||||||||||||||||
Reserved, RES0.
Indicates the maximum speculation depth of the instruction trace element stream. This is the maximum number of P0 elements in the trace element stream that can be speculative at any time.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, TRCIDR8
(op0 = 0b10, op1 = 0b001, CRn = 0b0000, CRm = 0b0000, op2 = 0b110)
if !(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if CPACR_EL1().TTA == '1' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().TRCID == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCIDR8(); end; elsif PSTATE.EL == EL2 then if CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCIDR8(); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TTA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCIDR8(); end; end;
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