Trace Buffer MPAM Configuration Register
Defines the PARTID, PMG, and MPAM_SP values used by the trace buffer unit in external mode.
AArch64 System register TRBMPAM_EL1 bits [63:0] are architecturally mapped to External register TRBMPAM_EL1[63:0].
This register is present only when FEAT_TRBE_MPAM is implemented. Otherwise, direct accesses to TRBMPAM_EL1 are UNDEFINED.
TRBMPAM_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | PMG | ||||||||||||||||||||||||||||||
| RES0 | EN | RES0 | PARTID | ||||||||||||||||||||||||||||
Reserved, RES0.
Performance Monitoring Group. Selects the PMG.
Only sufficient low-order bits are required to represent the TRBDEVID1.PMG_MAX. Higher-order bits are RES0.
This field is ignored by the PE when SelfHostedTraceEnabled() == TRUE.
The reset behavior of this field is:
Reserved, RES0.
Enable. Enables use of non-Default MPAM values.
| EN | Meaning |
|---|---|
| 0b0 |
Use Default physical PARTID and Default physical PMG values. |
| 0b1 |
Use TRBMPAM_EL1.{PARTID, PMG}. |
This field is ignored by the PE when SelfHostedTraceEnabled() == TRUE.
The reset behavior of this field is:
Reserved, RES0.
Partition Identifier. Selects the PARTID.
Only sufficient low-order bits are required to represent the TRBDEVID1.PARTID_MAX. Higher-order bits are RES0.
This field is ignored by the PE when SelfHostedTraceEnabled() == TRUE.
The reset behavior of this field is:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | EN | MPAM_SP | PMG | PARTID | |||||||||||||||||||||||||||
Reserved, RES0.
Enable. Enables use of non-Default MPAM values.
| EN | Meaning |
|---|---|
| 0b0 |
Use Default physical PARTID and Default physical PMG values, and the PARTID space corresponding to the trace physical address space defined by TRBMAR_EL1.PAS. |
| 0b1 |
Use TRBMPAM_EL1.{PARTID, PMG, MPAM_SP}. |
This field is ignored by the PE when SelfHostedTraceEnabled() == TRUE.
The reset behavior of this field is:
Partition Identifier space. Selects the PARTID space.
| MPAM_SP | Meaning | Applies when |
|---|---|---|
| 0b00 |
PARTID is in the Secure PARTID space. | When FEAT_Secure is implemented |
| 0b01 |
PARTID is in the Non-secure PARTID space. | |
| 0b10 |
PARTID is in the Root PARTID space. | When FEAT_RME is implemented |
| 0b11 |
PARTID is in the Realm PARTID space. | When FEAT_RME is implemented |
If the Trace Buffer Unit is using external mode and either TRBMPAM_EL1.MPAM_SP is set to reserved value, or the IMPLEMENTATION DEFINED authentication interface prohibits invasive debug of the Security state corresponding to the Partition Identifier space selected by TRBMPAM_EL1.MPAM_SP, then when the Trace Buffer Unit receives trace data from the trace unit, it does not write the trace data to memory and generates a trace buffer management event.
The interface prohibits invasive debug of the Security state if any of the following apply:
This field is ignored by the PE when SelfHostedTraceEnabled() == TRUE.
The reset behavior of this field is:
Performance Monitoring Group. Selects the PMG.
Only sufficient low-order bits are required to represent the TRBDEVID1.PMG_MAX. Higher-order bits are RES0.
This field is ignored by the PE when SelfHostedTraceEnabled() == TRUE.
The reset behavior of this field is:
Partition Identifier. Selects the PARTID.
Only sufficient low-order bits are required to represent the TRBDEVID1.PARTID_MAX. Higher-order bits are RES0.
This field is ignored by the PE when SelfHostedTraceEnabled() == TRUE.
The reset behavior of this field is:
The PE might ignore a write to TRBMPAM_EL1 if any of the following apply:
TRBLIMITR_EL1.E is 1, and either FEAT_TRBE_EXT is not implemented or the Trace Buffer Unit is using Self-hosted mode.
TRBLIMITR_EL1.XE is 1, FEAT_TRBE_EXT is implemented, and the Trace Buffer Unit is using External mode.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, TRBMPAM_EL1
(op0 = 0b11, op1 = 0b000, CRn = 0b1001, CRm = 0b1011, op2 = 0b101)
if !IsFeatureImplemented(FEAT_TRBE_MPAM) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnTB2 == '0' then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSTBTrap() then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGRTR2_EL2().nTRBMPAM_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().E2TB IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnTB2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRBMPAM_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().EnTB2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRBMPAM_EL1(); end; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRBMPAM_EL1(); end; end;
MSR TRBMPAM_EL1, <Xt>
(op0 = 0b11, op1 = 0b000, CRn = 0b1001, CRm = 0b1011, op2 = 0b101)
if !IsFeatureImplemented(FEAT_TRBE_MPAM) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnTB2 == '0' then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSTBTrap() then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGWTR2_EL2().nTRBMPAM_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().E2TB IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnTB2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRBMPAM_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().EnTB2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRBMPAM_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRBMPAM_EL1() = X{64}(t); end; end;
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