TPIDR_EL3 | Jon's Arm Reference

Provides a location where software executing at EL3 can store thread identifying information, for OS management purposes.

The PE makes no use of this register.

Configuration

This register is present only when EL3 is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to TPIDR_EL3 are UNDEFINED.

Attributes

Field descriptions

ThreadID, bits [63:0]:

Thread ID. Thread identifying information stored by software running at this Exception level.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TPIDR_EL3

(op0 = 0b11, op1 = 0b110, CRn = 0b1101, CRm = 0b0000, op2 = 0b010)

MSR TPIDR_EL3, <Xt>

(op0 = 0b11, op1 = 0b110, CRn = 0b1101, CRm = 0b0000, op2 = 0b010)

if !(HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_FGWTE3) && FGWTE3_EL3.TPIDR_EL3 == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else TPIDR_EL3 = X[t, 64];

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ThreadID
ThreadID