TLBI Domains Identification Register (EL1)
Provides information on how many bits of the TLBID field are implemented for TLBI IS and TLBI OS instructions.
This register is present only when FEAT_TLBID is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to TLBIDIDR_EL1 are UNDEFINED.
TLBIDIDR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | NVOS | RES0 | NOS | ||||||||||||||||||||||||||||
| RES0 | NVIS | RES0 | NIS | ||||||||||||||||||||||||||||
Reserved, RES0.
Number of bits of Virtual TLBI Domain supported for Outer Shareable TLBI instructions.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| NVOS | Meaning |
|---|---|
| 0b00000 |
There are no Virtual TLBI Domain Outer shareable bits. |
| 0b00001..0b00101 |
The number of Virtual TLBI Domain Outer shareable bits. |
The permitted values of this field depend on the value of NOS, as follows:
If NOS is 0, NVOS is 0.
If NOS is between 1 and 8, NVOS is between 1 and 5.
If NOS is between 9 and 16, NVOS is between 1 and 4.
Access to this field is RO.
Reserved, RES0.
Number of bits of TLBI Domain supported for Outer Shareable TLBI instructions.
Values greater than 16 are reserved.
The value of this field additionally determines the width of the VTLBIDOS<n>_EL2.TD<m> fields, as follows:
The value of this field is an IMPLEMENTATION DEFINED choice of:
| NOS | Meaning |
|---|---|
| 0b00000 |
The VTLBIDOS<n>_EL2 registers are not implemented. |
| 0b00001..0b01000 |
Each TD<m> field is 8 bits wide. NVOS is between 0 and 5. |
| 0b01001..0b10000 |
Each TD<m> field is 16 bits wide. NVOS must be between 0 and 4. |
Access to this field is RO.
Reserved, RES0.
Number of bits of Virtual TLBI Domain supported for Inner Shareable TLBI instructions.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| NVIS | Meaning |
|---|---|
| 0b00000 |
There are no Virtual TLBI Domain Inner shareable bits. |
| 0b00001..0b00101 |
The number of Virtual TLBI Domain Inner shareable bits. |
The permitted values of this field depend on the value of NIS, as follows:
If NIS is 0, NVIS is 0.
If NIS is between 1 and 8, NVIS is between 1 and 5.
If NIS is between 9 and 16, NVIS is between 1 and 4.
Access to this field is RO.
Reserved, RES0.
Number of bits of TLBI Domain supported for Inner Shareable TLBI instructions.
Values greater than 16 are reserved.
The value of this field additionally determines the width of the VTLBID<n>_EL2.TD<m> fields, as follows:
The value of this field is an IMPLEMENTATION DEFINED choice of:
| NIS | Meaning |
|---|---|
| 0b00000 |
The VTLBID<n>_EL2 registers are not implemented. |
| 0b00001..0b01000 |
Each TD<m> field is 8 bits wide. NVIS is between 0 and 5. |
| 0b01001..0b10000 |
Each TD<m> field is 16 bits wide. NVIS is between 0 and 4. |
Access to this field is RO.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, TLBIDIDR_EL1
(op0 = 0b11, op1 = 0b000, CRn = 0b1010, CRm = 0b0100, op2 = 0b110)
if !(IsFeatureImplemented(FEAT_TLBID) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && SCR_EL3().VTLBIDEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGRTR2_EL2().nTLBIDIDR_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().VTLBIDEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = TLBIDIDR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().VTLBIDEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = TLBIDIDR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = TLBIDIDR_EL1(); end;
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