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TFSR_EL3

Tag Fault Status Register (EL3)

Holds accumulated Tag Check Faults occurring at EL3 that are not taken precisely.

Configuration

This register is present only when FEAT_MTE_ASYNC is implemented or FEAT_MTE2 is implemented. Otherwise, direct accesses to TFSR_EL3 are UNDEFINED.

Attributes

TFSR_EL3 is a 64-bit register.

Field descriptions

When FEAT_MTE_ASYNC is not implemented:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RAZ
RAZ

Bits [63:0]:

Reserved, RAZ.

Otherwise:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0TF0

Bits [63:1]:

Reserved, RES0.

TF0, bit [0]:

Tag Check Fault. Asynchronously set to 1 when a Tag Check Fault using a virtual address with bit[55] == '0' occurs.

The reset behavior of this field is:

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TFSR_EL3

(op0 = 0b11, op1 = 0b110, CRn = 0b0101, CRm = 0b0110, op2 = 0b000)

if !(IsFeatureImplemented(FEAT_MTE_ASYNC) || IsFeatureImplemented(FEAT_MTE2)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then X{64}(t) = TFSR_EL3(); end;

MSR TFSR_EL3, <Xt>

(op0 = 0b11, op1 = 0b110, CRn = 0b0101, CRm = 0b0110, op2 = 0b000)

if !(IsFeatureImplemented(FEAT_MTE_ASYNC) || IsFeatureImplemented(FEAT_MTE2)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then TFSR_EL3() = X{64}(t); end;


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