Tag Fault Status Register (EL1)
Holds accumulated Tag Check Faults occurring at EL1 that are not taken precisely.
This register is present only when FEAT_MTE_ASYNC is implemented or FEAT_MTE2 is implemented. Otherwise, direct accesses to TFSR_EL1 are UNDEFINED.
TFSR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RAZ | |||||||||||||||||||||||||||||||
| RAZ | |||||||||||||||||||||||||||||||
Reserved, RAZ.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | TF1 | TF0 | |||||||||||||||||||||||||||||
Reserved, RES0.
Tag Check Fault. Asynchronously set to 1 when a Tag Check Fault using a virtual address with bit[55] == '1' occurs.
The reset behavior of this field is:
Tag Check Fault. Asynchronously set to 1 when a Tag Check Fault using a virtual address with bit[55] == '0' occurs.
The reset behavior of this field is:
When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name TFSR_EL1 or TFSR_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, TFSR_EL1
(op0 = 0b11, op1 = 0b000, CRn = 0b0101, CRm = 0b0110, op2 = 0b000)
if !(IsFeatureImplemented(FEAT_MTE_ASYNC) || IsFeatureImplemented(FEAT_MTE2)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '011' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && !(IsFeatureImplemented(FEAT_MTE2) && HCR_EL2().ATA == '1') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x190); else X{64}(t) = TFSR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = TFSR_EL2(); else X{64}(t) = TFSR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = TFSR_EL1(); end;
MSR TFSR_EL1, <Xt>
(op0 = 0b11, op1 = 0b000, CRn = 0b0101, CRm = 0b0110, op2 = 0b000)
if !(IsFeatureImplemented(FEAT_MTE_ASYNC) || IsFeatureImplemented(FEAT_MTE2)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '011' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && !(IsFeatureImplemented(FEAT_MTE2) && HCR_EL2().ATA == '1') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x190) = X{64}(t); else TFSR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then TFSR_EL2() = X{64}(t); else TFSR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then TFSR_EL1() = X{64}(t); end;
MRS <Xt>, TFSR_EL12
(op0 = 0b11, op1 = 0b101, CRn = 0b0101, CRm = 0b0110, op2 = 0b000)
if !(IsFeatureImplemented(FEAT_MTE_ASYNC) || IsFeatureImplemented(FEAT_MTE2)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X{64}(t) = NVMem(0x190); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = TFSR_EL1(); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = TFSR_EL1(); else Undefined(); end; end;
MSR TFSR_EL12, <Xt>
(op0 = 0b11, op1 = 0b101, CRn = 0b0101, CRm = 0b0110, op2 = 0b000)
if !(IsFeatureImplemented(FEAT_MTE_ASYNC) || IsFeatureImplemented(FEAT_MTE2)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem(0x190) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else TFSR_EL1() = X{64}(t); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then TFSR_EL1() = X{64}(t); else Undefined(); end; end;
MRS <Xt>, TFSR_EL2
(op0 = 0b11, op1 = 0b100, CRn = 0b0101, CRm = 0b0110, op2 = 0b000)
if !(IsFeatureImplemented(FEAT_MTE_ASYNC) || IsFeatureImplemented(FEAT_MTE2)) then Undefined(); elsif HaveEL(EL3) && ((PSTATE.EL == EL1 && EffectiveHCR_EL2_NVx() IN {'1x1'}) || PSTATE.EL == EL2) && EL3SDDUndefPriority() && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then if EL2Enabled() && !ELIsInHost(EL0) && !(IsFeatureImplemented(FEAT_MTE2) && HCR_EL2().ATA == '1') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = TFSR_EL1(); end; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = TFSR_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = TFSR_EL2(); end;
MSR TFSR_EL2, <Xt>
(op0 = 0b11, op1 = 0b100, CRn = 0b0101, CRm = 0b0110, op2 = 0b000)
if !(IsFeatureImplemented(FEAT_MTE_ASYNC) || IsFeatureImplemented(FEAT_MTE2)) then Undefined(); elsif HaveEL(EL3) && ((PSTATE.EL == EL1 && EffectiveHCR_EL2_NVx() IN {'1x1'}) || PSTATE.EL == EL2) && EL3SDDUndefPriority() && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then if EL2Enabled() && !ELIsInHost(EL0) && !(IsFeatureImplemented(FEAT_MTE2) && HCR_EL2().ATA == '1') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else TFSR_EL1() = X{64}(t); end; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else TFSR_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then TFSR_EL2() = X{64}(t); end;
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