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TCRMASK_EL1

Translation Control Masking Register (EL1)

Mask register to prevent updates of fields in TCR_EL1 on writes to TCR_EL1 or TCRALIAS_EL1.

Configuration

This register is present only when FEAT_SRMASK is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to TCRMASK_EL1 are UNDEFINED.

Attributes

TCRMASK_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0MTX1MTX0DSTCMA1TCMA0E0PD1E0PD0NFD1NFD0TBID1TBID0HWU162HWU161HWU160HWU159HWU062HWU061HWU060HWU059HPD1HPD0HDHATBI1TBI0ASRES0IPS
RES0TG1RES0SH1RES0ORGN1RES0IRGN1EPD1A1RES0T1SZRES0TG0RES0SH0RES0ORGN0RES0IRGN0EPD0RES0T0SZ

Bits [63:62]:

Reserved, RES0.

MTX1, bit [61] when FEAT_MTE_NO_ADDRESS_TAGS is implemented or FEAT_MTE_CANONICAL_TAGS is implemented:

Mask bit for MTX1.

MTX1Meaning
0b0

TCR_EL1.MTX1 is writable.

0b1

TCR_EL1.MTX1 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

MTX0, bit [60] when FEAT_MTE_NO_ADDRESS_TAGS is implemented or FEAT_MTE_CANONICAL_TAGS is implemented:

Mask bit for MTX0.

MTX0Meaning
0b0

TCR_EL1.MTX0 is writable.

0b1

TCR_EL1.MTX0 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

DS, bit [59] when FEAT_LPA2 is implemented:

Mask bit for DS.

DSMeaning
0b0

TCR_EL1.DS is writable.

0b1

TCR_EL1.DS is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TCMA1, bit [58] when FEAT_MTE2 is implemented:

Mask bit for TCMA1.

TCMA1Meaning
0b0

TCR_EL1.TCMA1 is writable.

0b1

TCR_EL1.TCMA1 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TCMA0, bit [57] when FEAT_MTE2 is implemented:

Mask bit for TCMA0.

TCMA0Meaning
0b0

TCR_EL1.TCMA0 is writable.

0b1

TCR_EL1.TCMA0 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

E0PD1, bit [56] when FEAT_E0PD is implemented:

Mask bit for E0PD1.

E0PD1Meaning
0b0

TCR_EL1.E0PD1 is writable.

0b1

TCR_EL1.E0PD1 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

E0PD0, bit [55] when FEAT_E0PD is implemented:

Mask bit for E0PD0.

E0PD0Meaning
0b0

TCR_EL1.E0PD0 is writable.

0b1

TCR_EL1.E0PD0 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

NFD1, bit [54] when FEAT_SVE is implemented:

Mask bit for NFD1.

NFD1Meaning
0b0

TCR_EL1.NFD1 is writable.

0b1

TCR_EL1.NFD1 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

NFD0, bit [53] when FEAT_SVE is implemented:

Mask bit for NFD0.

NFD0Meaning
0b0

TCR_EL1.NFD0 is writable.

0b1

TCR_EL1.NFD0 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TBID1, bit [52] when FEAT_PAuth is implemented:

Mask bit for TBID1.

TBID1Meaning
0b0

TCR_EL1.TBID1 is writable.

0b1

TCR_EL1.TBID1 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TBID0, bit [51] when FEAT_PAuth is implemented:

Mask bit for TBID0.

TBID0Meaning
0b0

TCR_EL1.TBID0 is writable.

0b1

TCR_EL1.TBID0 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

HWU162, bit [50] when FEAT_HPDS2 is implemented:

Mask bit for HWU162.

HWU162Meaning
0b0

TCR_EL1.HWU162 is writable.

0b1

TCR_EL1.HWU162 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

HWU161, bit [49] when FEAT_HPDS2 is implemented:

Mask bit for HWU161.

HWU161Meaning
0b0

TCR_EL1.HWU161 is writable.

0b1

TCR_EL1.HWU161 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

HWU160, bit [48] when FEAT_HPDS2 is implemented:

Mask bit for HWU160.

HWU160Meaning
0b0

TCR_EL1.HWU160 is writable.

0b1

TCR_EL1.HWU160 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

HWU159, bit [47] when FEAT_HPDS2 is implemented:

Mask bit for HWU159.

HWU159Meaning
0b0

TCR_EL1.HWU159 is writable.

0b1

TCR_EL1.HWU159 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

HWU062, bit [46] when FEAT_HPDS2 is implemented:

Mask bit for HWU062.

HWU062Meaning
0b0

TCR_EL1.HWU062 is writable.

0b1

TCR_EL1.HWU062 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

HWU061, bit [45] when FEAT_HPDS2 is implemented:

Mask bit for HWU061.

HWU061Meaning
0b0

TCR_EL1.HWU061 is writable.

0b1

TCR_EL1.HWU061 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

HWU060, bit [44] when FEAT_HPDS2 is implemented:

Mask bit for HWU060.

HWU060Meaning
0b0

TCR_EL1.HWU060 is writable.

0b1

TCR_EL1.HWU060 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

HWU059, bit [43] when FEAT_HPDS2 is implemented:

Mask bit for HWU059.

HWU059Meaning
0b0

TCR_EL1.HWU059 is writable.

0b1

TCR_EL1.HWU059 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

HPD1, bit [42] when FEAT_HPDS is implemented:

Mask bit for HPD1.

HPD1Meaning
0b0

TCR_EL1.HPD1 is writable.

0b1

TCR_EL1.HPD1 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

HPD0, bit [41] when FEAT_HPDS is implemented:

Mask bit for HPD0.

HPD0Meaning
0b0

TCR_EL1.HPD0 is writable.

0b1

TCR_EL1.HPD0 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

HD, bit [40] when FEAT_HAFDBS is implemented:

Mask bit for HD.

HDMeaning
0b0

TCR_EL1.HD is writable.

0b1

TCR_EL1.HD is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

HA, bit [39] when FEAT_HAF is implemented:

Mask bit for HA.

HAMeaning
0b0

TCR_EL1.HA is writable.

0b1

TCR_EL1.HA is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TBI1, bit [38]:

Mask bit for TBI1.

TBI1Meaning
0b0

TCR_EL1.TBI1 is writable.

0b1

TCR_EL1.TBI1 is not writable.

The reset behavior of this field is:

TBI0, bit [37]:

Mask bit for TBI0.

TBI0Meaning
0b0

TCR_EL1.TBI0 is writable.

0b1

TCR_EL1.TBI0 is not writable.

The reset behavior of this field is:

AS, bit [36]:

Mask bit for AS.

ASMeaning
0b0

TCR_EL1.AS is writable.

0b1

TCR_EL1.AS is not writable.

The reset behavior of this field is:

Bits [35:33]:

Reserved, RES0.

IPS, bit [32]:

Mask bit for IPS.

IPSMeaning
0b0

TCR_EL1.IPS is writable.

0b1

TCR_EL1.IPS is not writable.

The reset behavior of this field is:

Bit [31]:

Reserved, RES0.

TG1, bit [30]:

Mask bit for TG1.

TG1Meaning
0b0

TCR_EL1.TG1 is writable.

0b1

TCR_EL1.TG1 is not writable.

The reset behavior of this field is:

Bit [29]:

Reserved, RES0.

SH1, bit [28]:

Mask bit for SH1.

SH1Meaning
0b0

TCR_EL1.SH1 is writable.

0b1

TCR_EL1.SH1 is not writable.

The reset behavior of this field is:

Bit [27]:

Reserved, RES0.

ORGN1, bit [26]:

Mask bit for ORGN1.

ORGN1Meaning
0b0

TCR_EL1.ORGN1 is writable.

0b1

TCR_EL1.ORGN1 is not writable.

The reset behavior of this field is:

Bit [25]:

Reserved, RES0.

IRGN1, bit [24]:

Mask bit for IRGN1.

IRGN1Meaning
0b0

TCR_EL1.IRGN1 is writable.

0b1

TCR_EL1.IRGN1 is not writable.

The reset behavior of this field is:

EPD1, bit [23]:

Mask bit for EPD1.

EPD1Meaning
0b0

TCR_EL1.EPD1 is writable.

0b1

TCR_EL1.EPD1 is not writable.

The reset behavior of this field is:

A1, bit [22]:

Mask bit for A1.

A1Meaning
0b0

TCR_EL1.A1 is writable.

0b1

TCR_EL1.A1 is not writable.

The reset behavior of this field is:

Bits [21:17]:

Reserved, RES0.

T1SZ, bit [16]:

Mask bit for T1SZ.

T1SZMeaning
0b0

TCR_EL1.T1SZ is writable.

0b1

TCR_EL1.T1SZ is not writable.

The reset behavior of this field is:

Bit [15]:

Reserved, RES0.

TG0, bit [14]:

Mask bit for TG0.

TG0Meaning
0b0

TCR_EL1.TG0 is writable.

0b1

TCR_EL1.TG0 is not writable.

The reset behavior of this field is:

Bit [13]:

Reserved, RES0.

SH0, bit [12]:

Mask bit for SH0.

SH0Meaning
0b0

TCR_EL1.SH0 is writable.

0b1

TCR_EL1.SH0 is not writable.

The reset behavior of this field is:

Bit [11]:

Reserved, RES0.

ORGN0, bit [10]:

Mask bit for ORGN0.

ORGN0Meaning
0b0

TCR_EL1.ORGN0 is writable.

0b1

TCR_EL1.ORGN0 is not writable.

The reset behavior of this field is:

Bit [9]:

Reserved, RES0.

IRGN0, bit [8]:

Mask bit for IRGN0.

IRGN0Meaning
0b0

TCR_EL1.IRGN0 is writable.

0b1

TCR_EL1.IRGN0 is not writable.

The reset behavior of this field is:

EPD0, bit [7]:

Mask bit for EPD0.

EPD0Meaning
0b0

TCR_EL1.EPD0 is writable.

0b1

TCR_EL1.EPD0 is not writable.

The reset behavior of this field is:

Bits [6:1]:

Reserved, RES0.

T0SZ, bit [0]:

Mask bit for T0SZ.

T0SZMeaning
0b0

TCR_EL1.T0SZ is writable.

0b1

TCR_EL1.T0SZ is not writable.

The reset behavior of this field is:

Access Instructions

When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name TCRMASK_EL1 or TCRMASK_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TCRMASK_EL1

(op0 = 0b11, op1 = 0b000, CRn = 0b0010, CRm = 0b0111, op2 = 0b010)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGRTR2_EL2().nTCRMASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x330); else X{64}(t) = TCRMASK_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = TCRMASK_EL2(); else X{64}(t) = TCRMASK_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = TCRMASK_EL1(); end;

MSR TCRMASK_EL1, <Xt>

(op0 = 0b11, op1 = 0b000, CRn = 0b0010, CRm = 0b0111, op2 = 0b010)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGWTR2_EL2().nTCRMASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x330) = X{64}(t); elsif !IsZero(TCRMASK_EL1()) then Undefined(); else TCRMASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then if !IsZero(TCRMASK_EL2()) then Undefined(); else TCRMASK_EL2() = X{64}(t); end; else TCRMASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then TCRMASK_EL1() = X{64}(t); end;

When FEAT_VHE is implemented:

MRS <Xt>, TCRMASK_EL12

(op0 = 0b11, op1 = 0b101, CRn = 0b0010, CRm = 0b0111, op2 = 0b010)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X{64}(t) = NVMem(0x330); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = TCRMASK_EL1(); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = TCRMASK_EL1(); else Undefined(); end; end;

When FEAT_VHE is implemented:

MSR TCRMASK_EL12, <Xt>

(op0 = 0b11, op1 = 0b101, CRn = 0b0010, CRm = 0b0111, op2 = 0b010)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem(0x330) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else TCRMASK_EL1() = X{64}(t); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then TCRMASK_EL1() = X{64}(t); else Undefined(); end; end;

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