TCO | Jon's Arm Reference

When FEAT_MTE is implemented, this register allows tag checks to be disabled globally.

When FEAT_MTE2 is not implemented, it is IMPLEMENTATION DEFINED if accesses to this register access PSTATE.TCO or are RAZ/WI.

Configuration

This register is present only when FEAT_MTE is implemented. Otherwise, direct accesses to TCO are UNDEFINED.

Attributes

Field descriptions

Bits [63:26]:

TCO, bit [25]:

Bits [24:0]:

TCO	Meaning
0b0	Loads and Stores are not affected by this control.
0b1	Loads and Stores are unchecked.

Access Instructions

For information about the operation of the MSR (immediate) accessor, see MSR (immediate).

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TCO

(op0 = 0b11, op1 = 0b011, CRn = 0b0100, CRm = 0b0010, op2 = 0b111)

if !IsFeatureImplemented(FEAT_MTE) then UNDEFINED; elsif PSTATE.EL == EL0 then X[t, 64] = Zeros(38):PSTATE.TCO:Zeros(25); elsif PSTATE.EL == EL1 then X[t, 64] = Zeros(38):PSTATE.TCO:Zeros(25); elsif PSTATE.EL == EL2 then X[t, 64] = Zeros(38):PSTATE.TCO:Zeros(25); elsif PSTATE.EL == EL3 then X[t, 64] = Zeros(38):PSTATE.TCO:Zeros(25);

MSR TCO, <Xt>

(op0 = 0b11, op1 = 0b011, CRn = 0b0100, CRm = 0b0010, op2 = 0b111)

if !IsFeatureImplemented(FEAT_MTE) then UNDEFINED; elsif PSTATE.EL == EL0 then PSTATE.TCO = X[t, 64]<25>; elsif PSTATE.EL == EL1 then PSTATE.TCO = X[t, 64]<25>; elsif PSTATE.EL == EL2 then PSTATE.TCO = X[t, 64]<25>; elsif PSTATE.EL == EL3 then PSTATE.TCO = X[t, 64]<25>;

MSR TCO, #<imm>

(op0 = 0b00, op1 = 0b011, CRn = 0b0100, op2 = 0b100)

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0						TCO	RES0