Stack Pointer Select
Allows the Stack Pointer to be selected between SP_EL0 and SP_ELx.
This register is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to SPSel are UNDEFINED.
SPSel is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | SP | ||||||||||||||||||||||||||||||
Reserved, RES0.
Stack pointer to use. Possible values of this bit are:
| SP | Meaning |
|---|---|
| 0b0 |
Use SP_EL0 at all Exception levels. |
| 0b1 | Use SP_ELx for Exception level ELx. When FEAT_NMI is implemented and SCTLR_ELx.SPINTMASK is 1, if execution is at ELx, an IRQ or FIQ interrupt that is targeted to ELx is masked regardless of any denotion of Superpriority. |
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, SPSel
(op0 = 0b11, op1 = 0b000, CRn = 0b0100, CRm = 0b0010, op2 = 0b000)
if !IsFeatureImplemented(FEAT_AA64) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then X[t, 64] = Zeros(63):PSTATE.SP; elsif PSTATE.EL == EL2 then X[t, 64] = Zeros(63):PSTATE.SP; elsif PSTATE.EL == EL3 then X[t, 64] = Zeros(63):PSTATE.SP;
MSR SPSel, <Xt>
(op0 = 0b11, op1 = 0b000, CRn = 0b0100, CRm = 0b0010, op2 = 0b000)
if !IsFeatureImplemented(FEAT_AA64) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then PSTATE.SP = X[t, 64]<0>; elsif PSTATE.EL == EL2 then PSTATE.SP = X[t, 64]<0>; elsif PSTATE.EL == EL3 then PSTATE.SP = X[t, 64]<0>;
MSR SPSel, #<imm>
(op0 = 0b00, op1 = 0b000, CRn = 0b0100, op2 = 0b101)
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