System Performance Monitors Event Count Register
Event counter <n> in System PMU <s>, where n is 0 to 63.
This register is present only when FEAT_SPMU is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to SPMEVCNTR<n>_EL0 are UNDEFINED.
SPMEVCNTR<n>_EL0 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CNTR | |||||||||||||||||||||||||||||||
| CNTR | |||||||||||||||||||||||||||||||
Event counter n.
The number of implemented bits for SPMEVCNTR<n>_EL0 is IMPLEMENTATION DEFINED. Unimplemented bits are RES0.
The reset behavior of this field is:
To access SPMEVCNTR<n>_EL0 for System PMU <s>, set SPMSELR_EL0.SYSPMUSEL to s and SPMSELR_EL0.BANK to n[5:4].
SPMEVCNTR<n>_EL0 reads-as-zero and ignores writes if any of the following are true:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, SPMEVCNTR<m>_EL0 ; Where m = 0-15
(op0 = 0b10, op1 = 0b011, CRn = 0b1110, CRm = 0b000:m[3], op2 = m[2:0])
let m:integer = UInt(CRm[0] :: op2[2:0]); if !(IsFeatureImplemented(FEAT_SPMU) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL != EL3 && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL != EL3 && EL3SDDUndefPriority() && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then Undefined(); elsif PSTATE.EL == EL0 then if MDSCR_EL1().EnSPM == '0' then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EffectivelyAtEL0NotInHost() && SPMACCESSR_EL1()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EL2Enabled() && EffectivelyAtEL0NotInHost() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGRTR2_EL2().nSPMEVCNTRn_EL0 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().EnSPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && SPMACCESSR_EL2()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !IsSPMUCounterImplemented(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) then X{64}(t) = Zeros{64}; else X{64}(t) = SPMEVCNTR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGRTR2_EL2().nSPMEVCNTRn_EL0 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().EnSPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && SPMACCESSR_EL2()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !IsSPMUCounterImplemented(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) then X{64}(t) = Zeros{64}; else X{64}(t) = SPMEVCNTR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !IsSPMUCounterImplemented(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) then X{64}(t) = Zeros{64}; else X{64}(t) = SPMEVCNTR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m); end; elsif PSTATE.EL == EL3 then if !IsSPMUCounterImplemented(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) then X{64}(t) = Zeros{64}; else X{64}(t) = SPMEVCNTR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m); end; end;
MSR SPMEVCNTR<m>_EL0, <Xt> ; Where m = 0-15
(op0 = 0b10, op1 = 0b011, CRn = 0b1110, CRm = 0b000:m[3], op2 = m[2:0])
let m:integer = UInt(CRm[0] :: op2[2:0]); if !(IsFeatureImplemented(FEAT_SPMU) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL != EL3 && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL != EL3 && EL3SDDUndefPriority() && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then Undefined(); elsif PSTATE.EL == EL0 then if MDSCR_EL1().EnSPM == '0' then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EffectivelyAtEL0NotInHost() && SPMACCESSR_EL1()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EL2Enabled() && EffectivelyAtEL0NotInHost() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGWTR2_EL2().nSPMEVCNTRn_EL0 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().EnSPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && SPMACCESSR_EL2()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !IsSPMUCounterImplemented(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) then return; else SPMEVCNTR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) = X{64}(t); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGWTR2_EL2().nSPMEVCNTRn_EL0 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().EnSPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && SPMACCESSR_EL2()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !IsSPMUCounterImplemented(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) then return; else SPMEVCNTR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !IsSPMUCounterImplemented(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) then return; else SPMEVCNTR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) = X{64}(t); end; elsif PSTATE.EL == EL3 then if !IsSPMUCounterImplemented(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) then return; else SPMEVCNTR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) = X{64}(t); end; end;
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