SCTLRMASK_EL2

This register is present only when FEAT_SRMASK is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to SCTLRMASK_EL2 are UNDEFINED.

This register has no effect if EL2 is not enabled in the current Security state.

Attributes

Field descriptions

TIDCP, bit [63] when FEAT_TIDCP1 is implemented:

TIDCP	Meaning
0b0	SCTLR_EL2.TIDCP is writable.
0b1	SCTLR_EL2.TIDCP is not writable.

Otherwise:

SPINTMASK, bit [62] when FEAT_NMI is implemented:

SPINTMASK	Meaning
0b0	SCTLR_EL2.SPINTMASK is writable.
0b1	SCTLR_EL2.SPINTMASK is not writable.

Otherwise:

NMI, bit [61] when FEAT_NMI is implemented:

NMI	Meaning
0b0	SCTLR_EL2.NMI is writable.
0b1	SCTLR_EL2.NMI is not writable.

Otherwise:

EnTP2, bit [60] when FEAT_SME is implemented:

EnTP2	Meaning
0b0	SCTLR_EL2.EnTP2 is writable.
0b1	SCTLR_EL2.EnTP2 is not writable.

Otherwise:

TCSO, bit [59] when FEAT_MTE_STORE_ONLY is implemented:

TCSO	Meaning
0b0	SCTLR_EL2.TCSO is writable.
0b1	SCTLR_EL2.TCSO is not writable.

Otherwise:

TCSO0, bit [58] when FEAT_MTE_STORE_ONLY is implemented:

TCSO0	Meaning
0b0	SCTLR_EL2.TCSO0 is writable.
0b1	SCTLR_EL2.TCSO0 is not writable.

Otherwise:

EPAN, bit [57] when FEAT_PAN3 is implemented:

EPAN	Meaning
0b0	SCTLR_EL2.EPAN is writable.
0b1	SCTLR_EL2.EPAN is not writable.

Otherwise:

EnALS, bit [56] when FEAT_LS64 is implemented:

EnALS	Meaning
0b0	SCTLR_EL2.EnALS is writable.
0b1	SCTLR_EL2.EnALS is not writable.

Otherwise:

EnAS0, bit [55] when FEAT_LS64_ACCDATA is implemented:

EnAS0	Meaning
0b0	SCTLR_EL2.EnAS0 is writable.
0b1	SCTLR_EL2.EnAS0 is not writable.

Otherwise:

EnASR, bit [54] when FEAT_LS64_V is implemented:

EnASR	Meaning
0b0	SCTLR_EL2.EnASR is writable.
0b1	SCTLR_EL2.EnASR is not writable.

Otherwise:

Bits [53:47]:

TWEDEL, bit [46] when FEAT_TWED is implemented:

TWEDEL	Meaning
0b0	SCTLR_EL2.TWEDEL is writable.
0b1	SCTLR_EL2.TWEDEL is not writable.

Otherwise:

TWEDEn, bit [45] when FEAT_TWED is implemented:

TWEDEn	Meaning
0b0	SCTLR_EL2.TWEDEn is writable.
0b1	SCTLR_EL2.TWEDEn is not writable.

Otherwise:

DSSBS, bit [44] when FEAT_SSBS is implemented:

DSSBS	Meaning
0b0	SCTLR_EL2.DSSBS is writable.
0b1	SCTLR_EL2.DSSBS is not writable.

Otherwise:

ATA, bit [43] when FEAT_MTE2 is implemented:

ATA	Meaning
0b0	SCTLR_EL2.ATA is writable.
0b1	SCTLR_EL2.ATA is not writable.

Otherwise:

ATA0, bit [42] when FEAT_MTE2 is implemented:

ATA0	Meaning
0b0	SCTLR_EL2.ATA0 is writable.
0b1	SCTLR_EL2.ATA0 is not writable.

Otherwise:

Bit [41]:

TCF, bit [40] when FEAT_MTE2 is implemented:

TCF	Meaning
0b0	SCTLR_EL2.TCF is writable.
0b1	SCTLR_EL2.TCF is not writable.

Otherwise:

Bit [39]:

TCF0, bit [38] when FEAT_MTE2 is implemented:

TCF0	Meaning
0b0	SCTLR_EL2.TCF0 is writable.
0b1	SCTLR_EL2.TCF0 is not writable.

Otherwise:

ITFSB, bit [37] when FEAT_MTE_ASYNC is implemented:

ITFSB	Meaning
0b0	SCTLR_EL2.ITFSB is writable.
0b1	SCTLR_EL2.ITFSB is not writable.

Otherwise:

BT, bit [36] when FEAT_BTI is implemented:

BT	Meaning
0b0	SCTLR_EL2.BT is writable.
0b1	SCTLR_EL2.BT is not writable.

Otherwise:

BT0, bit [35] when FEAT_BTI is implemented:

BT0	Meaning
0b0	SCTLR_EL2.BT0 is writable.
0b1	SCTLR_EL2.BT0 is not writable.

Otherwise:

EnFPM, bit [34] when FEAT_FPMR is implemented:

EnFPM	Meaning
0b0	SCTLR_EL2.EnFPM is writable.
0b1	SCTLR_EL2.EnFPM is not writable.

Otherwise:

MSCEn, bit [33] when FEAT_MOPS is implemented:

MSCEn	Meaning
0b0	SCTLR_EL2.MSCEn is writable.
0b1	SCTLR_EL2.MSCEn is not writable.

Otherwise:

CMOW, bit [32] when FEAT_CMOW is implemented:

CMOW	Meaning
0b0	SCTLR_EL2.CMOW is writable.
0b1	SCTLR_EL2.CMOW is not writable.

Otherwise:

EnIA, bit [31] when FEAT_PAuth is implemented:

EnIA	Meaning
0b0	SCTLR_EL2.EnIA is writable.
0b1	SCTLR_EL2.EnIA is not writable.

Otherwise:

EnIB, bit [30] when FEAT_PAuth is implemented:

EnIB	Meaning
0b0	SCTLR_EL2.EnIB is writable.
0b1	SCTLR_EL2.EnIB is not writable.

Otherwise:

LSMAOE, bit [29] when FEAT_LSMAOC is implemented:

LSMAOE	Meaning
0b0	SCTLR_EL2.LSMAOE is writable.
0b1	SCTLR_EL2.LSMAOE is not writable.

Otherwise:

nTLSMD, bit [28] when FEAT_LSMAOC is implemented:

nTLSMD	Meaning
0b0	SCTLR_EL2.nTLSMD is writable.
0b1	SCTLR_EL2.nTLSMD is not writable.

Otherwise:

EnDA, bit [27] when FEAT_PAuth is implemented:

EnDA	Meaning
0b0	SCTLR_EL2.EnDA is writable.
0b1	SCTLR_EL2.EnDA is not writable.

Otherwise:

UCI, bit [26]:

UCI	Meaning
0b0	SCTLR_EL2.UCI is writable.
0b1	SCTLR_EL2.UCI is not writable.

EE, bit [25] when FEAT_MixedEnd is implemented:

EE	Meaning
0b0	SCTLR_EL2.EE is writable.
0b1	SCTLR_EL2.EE is not writable.

Otherwise:

E0E, bit [24] when FEAT_MixedEndEL0 is implemented:

E0E	Meaning
0b0	SCTLR_EL2.E0E is writable.
0b1	SCTLR_EL2.E0E is not writable.

Otherwise:

SPAN, bit [23]:

SPAN	Meaning
0b0	SCTLR_EL2.SPAN is writable.
0b1	SCTLR_EL2.SPAN is not writable.

EIS, bit [22] when FEAT_ExS is implemented:

EIS	Meaning
0b0	SCTLR_EL2.EIS is writable.
0b1	SCTLR_EL2.EIS is not writable.

Otherwise:

IESB, bit [21] when FEAT_IESB is implemented:

IESB	Meaning
0b0	SCTLR_EL2.IESB is writable.
0b1	SCTLR_EL2.IESB is not writable.

Otherwise:

TSCXT, bit [20] when FEAT_CSV2_2 is implemented or FEAT_CSV2_1p2 is implemented:

TSCXT	Meaning
0b0	SCTLR_EL2.TSCXT is writable.
0b1	SCTLR_EL2.TSCXT is not writable.

Otherwise:

WXN, bit [19]:

nTWE, bit [18]:

Bit [17]:

nTWI, bit [16]:

UCT, bit [15]:

DZE, bit [14]:

WXN	Meaning
0b0	SCTLR_EL2.WXN is writable.
0b1	SCTLR_EL2.WXN is not writable.

nTWE	Meaning
0b0	SCTLR_EL2.nTWE is writable.
0b1	SCTLR_EL2.nTWE is not writable.

nTWI	Meaning
0b0	SCTLR_EL2.nTWI is writable.
0b1	SCTLR_EL2.nTWI is not writable.

UCT	Meaning
0b0	SCTLR_EL2.UCT is writable.
0b1	SCTLR_EL2.UCT is not writable.

DZE	Meaning
0b0	SCTLR_EL2.DZE is writable.
0b1	SCTLR_EL2.DZE is not writable.

EnDB, bit [13] when FEAT_PAuth is implemented:

EnDB	Meaning
0b0	SCTLR_EL2.EnDB is writable.
0b1	SCTLR_EL2.EnDB is not writable.

Otherwise:

I, bit [12]:

I	Meaning
0b0	SCTLR_EL2.I is writable.
0b1	SCTLR_EL2.I is not writable.

EOS, bit [11] when FEAT_ExS is implemented:

EOS	Meaning
0b0	SCTLR_EL2.EOS is writable.
0b1	SCTLR_EL2.EOS is not writable.

Otherwise:

EnRCTX, bit [10] when FEAT_SPECRES is implemented:

EnRCTX	Meaning
0b0	SCTLR_EL2.EnRCTX is writable.
0b1	SCTLR_EL2.EnRCTX is not writable.

Otherwise:

Bit [9]:

SED, bit [8] when FEAT_AA32EL0 is implemented:

SED	Meaning
0b0	SCTLR_EL2.SED is writable.
0b1	SCTLR_EL2.SED is not writable.

Otherwise:

ITD, bit [7] when FEAT_AA32EL0 is implemented:

ITD	Meaning
0b0	SCTLR_EL2.ITD is writable.
0b1	SCTLR_EL2.ITD is not writable.

Otherwise:

nAA, bit [6]:

nAA	Meaning
0b0	SCTLR_EL2.nAA is writable.
0b1	SCTLR_EL2.nAA is not writable.

CP15BEN, bit [5] when FEAT_AA32EL0 is implemented:

CP15BEN	Meaning
0b0	SCTLR_EL2.CP15BEN is writable.
0b1	SCTLR_EL2.CP15BEN is not writable.

Otherwise:

SA0, bit [4]:

SA, bit [3]:

C, bit [2]:

A, bit [1]:

M, bit [0]:

SA0	Meaning
0b0	SCTLR_EL2.SA0 is writable.
0b1	SCTLR_EL2.SA0 is not writable.

Access Instructions

When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name SCTLRMASK_EL2 or SCTLRMASK_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SCTLRMASK_EL2

(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0100, op2 = 0b000)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = SCTLRMASK_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = SCTLRMASK_EL2(); end;

MSR SCTLRMASK_EL2, <Xt>

(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0100, op2 = 0b000)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !IsZero(SCTLRMASK_EL2()) then Undefined(); else SCTLRMASK_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then SCTLRMASK_EL2() = X{64}(t); end;

MRS <Xt>, SCTLRMASK_EL1

(op0 = 0b11, op1 = 0b000, CRn = 0b0001, CRm = 0b0100, op2 = 0b000)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGRTR2_EL2().nSCTLRMASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x318); else X{64}(t) = SCTLRMASK_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = SCTLRMASK_EL2(); else X{64}(t) = SCTLRMASK_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = SCTLRMASK_EL1(); end;

MSR SCTLRMASK_EL1, <Xt>

(op0 = 0b11, op1 = 0b000, CRn = 0b0001, CRm = 0b0100, op2 = 0b000)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGWTR2_EL2().nSCTLRMASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x318) = X{64}(t); elsif !IsZero(SCTLRMASK_EL1()) then Undefined(); else SCTLRMASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then if !IsZero(SCTLRMASK_EL2()) then Undefined(); else SCTLRMASK_EL2() = X{64}(t); end; else SCTLRMASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then SCTLRMASK_EL1() = X{64}(t); end;

SA	Meaning
0b0	SCTLR_EL2.SA is writable.
0b1	SCTLR_EL2.SA is not writable.

Configuration

Attributes

Field descriptions

TIDCP, bit [63] when FEAT_TIDCP1 is implemented:

Otherwise:

SPINTMASK, bit [62] when FEAT_NMI is implemented:

Otherwise:

NMI, bit [61] when FEAT_NMI is implemented:

Otherwise:

EnTP2, bit [60] when FEAT_SME is implemented:

Otherwise:

TCSO, bit [59] when FEAT_MTE_STORE_ONLY is implemented:

Otherwise:

TCSO0, bit [58] when FEAT_MTE_STORE_ONLY is implemented:

Otherwise:

EPAN, bit [57] when FEAT_PAN3 is implemented:

Otherwise:

EnALS, bit [56] when FEAT_LS64 is implemented:

Otherwise:

EnAS0, bit [55] when FEAT_LS64_ACCDATA is implemented:

Otherwise:

EnASR, bit [54] when FEAT_LS64_V is implemented:

Otherwise:

Bits [53:47]:

TWEDEL, bit [46] when FEAT_TWED is implemented:

Otherwise:

TWEDEn, bit [45] when FEAT_TWED is implemented:

Otherwise:

DSSBS, bit [44] when FEAT_SSBS is implemented:

Otherwise:

ATA, bit [43] when FEAT_MTE2 is implemented:

Otherwise:

ATA0, bit [42] when FEAT_MTE2 is implemented:

Otherwise:

Bit [41]:

TCF, bit [40] when FEAT_MTE2 is implemented:

Otherwise:

Bit [39]:

TCF0, bit [38] when FEAT_MTE2 is implemented:

Otherwise:

ITFSB, bit [37] when FEAT_MTE_ASYNC is implemented:

Otherwise:

BT, bit [36] when FEAT_BTI is implemented:

Otherwise:

BT0, bit [35] when FEAT_BTI is implemented:

Otherwise:

EnFPM, bit [34] when FEAT_FPMR is implemented:

Otherwise:

MSCEn, bit [33] when FEAT_MOPS is implemented:

Otherwise:

CMOW, bit [32] when FEAT_CMOW is implemented:

Otherwise:

EnIA, bit [31] when FEAT_PAuth is implemented:

Otherwise:

EnIB, bit [30] when FEAT_PAuth is implemented:

Otherwise:

LSMAOE, bit [29] when FEAT_LSMAOC is implemented:

Otherwise:

nTLSMD, bit [28] when FEAT_LSMAOC is implemented:

Otherwise:

EnDA, bit [27] when FEAT_PAuth is implemented:

Otherwise:

UCI, bit [26]:

EE, bit [25] when FEAT_MixedEnd is implemented:

Otherwise:

E0E, bit [24] when FEAT_MixedEndEL0 is implemented:

Otherwise:

SPAN, bit [23]:

EIS, bit [22] when FEAT_ExS is implemented:

Otherwise:

IESB, bit [21] when FEAT_IESB is implemented:

Otherwise:

TSCXT, bit [20] when FEAT_CSV2_2 is implemented or FEAT_CSV2_1p2 is implemented:

Otherwise:

WXN, bit [19]:

nTWE, bit [18]:

Bit [17]:

nTWI, bit [16]:

UCT, bit [15]: