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SCTLR2MASK_EL1

Extended System Control Masking Register (EL1)

Mask register to prevent updates of fields in SCTLR2_EL1 on writes to SCTLR2_EL1 or SCTLR2ALIAS_EL1.

Configuration

This register is present only when FEAT_SRMASK is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to SCTLR2MASK_EL1 are UNDEFINED.

Attributes

SCTLR2MASK_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0TLBOSNISFDITBTDBTD0EnIA2EnIB2EnDA2EnDB2RES0CPTM0CPTMCPTA0CPTAEnPACM0EnPACMEnIDCP128EASEEnANERREnADERRNMEARES0

Bits [63:27]:

Reserved, RES0.

TLBOSNIS, bit [26] when FEAT_TLBID is implemented:

Mask bit for TLBOSNIS.

TLBOSNISMeaning
0b0

SCTLR2_EL1.TLBOSNIS is writable.

0b1

SCTLR2_EL1.TLBOSNIS is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

FDIT, bit [25] when FEAT_FDIT is implemented:

Mask bit for FDIT.

FDITMeaning
0b0

SCTLR2_EL1.FDIT is writable.

0b1

SCTLR2_EL1.FDIT is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

BTD, bit [24] when FEAT_PAuth_EnhCtl is implemented:

Mask bit for BTD.

BTDMeaning
0b0

SCTLR2_EL1.BTD is writable.

0b1

SCTLR2_EL1.BTD is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

BTD0, bit [23] when FEAT_PAuth_EnhCtl is implemented:

Mask bit for BTD0.

BTD0Meaning
0b0

SCTLR2_EL1.BTD0 is writable.

0b1

SCTLR2_EL1.BTD0 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

EnIA2, bit [22] when FEAT_PAuth_EnhCtl is implemented:

Mask bit for EnIA2.

EnIA2Meaning
0b0

SCTLR2_EL1.EnIA2 is writable.

0b1

SCTLR2_EL1.EnIA2 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

EnIB2, bit [21] when FEAT_PAuth_EnhCtl is implemented:

Mask bit for EnIB2.

EnIB2Meaning
0b0

SCTLR2_EL1.EnIB2 is writable.

0b1

SCTLR2_EL1.EnIB2 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

EnDA2, bit [20] when FEAT_PAuth_EnhCtl is implemented:

Mask bit for EnDA2.

EnDA2Meaning
0b0

SCTLR2_EL1.EnDA2 is writable.

0b1

SCTLR2_EL1.EnDA2 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

EnDB2, bit [19] when FEAT_PAuth_EnhCtl is implemented:

Mask bit for EnDB2.

EnDB2Meaning
0b0

SCTLR2_EL1.EnDB2 is writable.

0b1

SCTLR2_EL1.EnDB2 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [18:13]:

Reserved, RES0.

CPTM0, bit [12] when FEAT_CPA2 is implemented:

Mask bit for CPTM0.

CPTM0Meaning
0b0

SCTLR2_EL1.CPTM0 is writable.

0b1

SCTLR2_EL1.CPTM0 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

CPTM, bit [11] when FEAT_CPA2 is implemented:

Mask bit for CPTM.

CPTMMeaning
0b0

SCTLR2_EL1.CPTM is writable.

0b1

SCTLR2_EL1.CPTM is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

CPTA0, bit [10] when FEAT_CPA2 is implemented:

Mask bit for CPTA0.

CPTA0Meaning
0b0

SCTLR2_EL1.CPTA0 is writable.

0b1

SCTLR2_EL1.CPTA0 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

CPTA, bit [9] when FEAT_CPA2 is implemented:

Mask bit for CPTA.

CPTAMeaning
0b0

SCTLR2_EL1.CPTA is writable.

0b1

SCTLR2_EL1.CPTA is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

EnPACM0, bit [8] when FEAT_PAuth_LR is implemented:

Mask bit for EnPACM0.

EnPACM0Meaning
0b0

SCTLR2_EL1.EnPACM0 is writable.

0b1

SCTLR2_EL1.EnPACM0 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

EnPACM, bit [7] when FEAT_PAuth_LR is implemented:

Mask bit for EnPACM.

EnPACMMeaning
0b0

SCTLR2_EL1.EnPACM is writable.

0b1

SCTLR2_EL1.EnPACM is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

EnIDCP128, bit [6] when FEAT_SYSREG128 is implemented:

Mask bit for EnIDCP128.

EnIDCP128Meaning
0b0

SCTLR2_EL1.EnIDCP128 is writable.

0b1

SCTLR2_EL1.EnIDCP128 is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

EASE, bit [5] when FEAT_DoubleFault2 is implemented:

Mask bit for EASE.

EASEMeaning
0b0

SCTLR2_EL1.EASE is writable.

0b1

SCTLR2_EL1.EASE is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

EnANERR, bit [4] when FEAT_ANERR is implemented:

Mask bit for EnANERR.

EnANERRMeaning
0b0

SCTLR2_EL1.EnANERR is writable.

0b1

SCTLR2_EL1.EnANERR is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

EnADERR, bit [3] when FEAT_ADERR is implemented:

Mask bit for EnADERR.

EnADERRMeaning
0b0

SCTLR2_EL1.EnADERR is writable.

0b1

SCTLR2_EL1.EnADERR is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

NMEA, bit [2] when FEAT_DoubleFault2 is implemented:

Mask bit for NMEA.

NMEAMeaning
0b0

SCTLR2_EL1.NMEA is writable.

0b1

SCTLR2_EL1.NMEA is not writable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [1:0]:

Reserved, RES0.

Access Instructions

When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name SCTLR2MASK_EL1 or SCTLR2MASK_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SCTLR2MASK_EL1

(op0 = 0b11, op1 = 0b000, CRn = 0b0001, CRm = 0b0100, op2 = 0b011)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGRTR2_EL2().nSCTLR2MASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x328); else X{64}(t) = SCTLR2MASK_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = SCTLR2MASK_EL2(); else X{64}(t) = SCTLR2MASK_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = SCTLR2MASK_EL1(); end;

MSR SCTLR2MASK_EL1, <Xt>

(op0 = 0b11, op1 = 0b000, CRn = 0b0001, CRm = 0b0100, op2 = 0b011)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGWTR2_EL2().nSCTLR2MASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x328) = X{64}(t); elsif !IsZero(SCTLR2MASK_EL1()) then Undefined(); else SCTLR2MASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then if !IsZero(SCTLR2MASK_EL2()) then Undefined(); else SCTLR2MASK_EL2() = X{64}(t); end; else SCTLR2MASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then SCTLR2MASK_EL1() = X{64}(t); end;

When FEAT_VHE is implemented:

MRS <Xt>, SCTLR2MASK_EL12

(op0 = 0b11, op1 = 0b101, CRn = 0b0001, CRm = 0b0100, op2 = 0b011)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X{64}(t) = NVMem(0x328); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = SCTLR2MASK_EL1(); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = SCTLR2MASK_EL1(); else Undefined(); end; end;

When FEAT_VHE is implemented:

MSR SCTLR2MASK_EL12, <Xt>

(op0 = 0b11, op1 = 0b101, CRn = 0b0001, CRm = 0b0100, op2 = 0b011)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem(0x328) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else SCTLR2MASK_EL1() = X{64}(t); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then SCTLR2MASK_EL1() = X{64}(t); else Undefined(); end; end;

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