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PMXEVTYPER_EL0

Performance Monitors Selected Event Type Register

When PMSELR_EL0.SEL selects an event counter, this accesses a PMEVTYPER<n>_EL0 register. When PMSELR_EL0.SEL selects the cycle counter, this accesses PMCCFILTR_EL0.

Configuration

AArch64 System register PMXEVTYPER_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMXEVTYPER[31:0].

This register is present only when FEAT_PMUv3 is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to PMXEVTYPER_EL0 are UNDEFINED.

Attributes

PMXEVTYPER_EL0 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
EVTYPERn
EVTYPERn

EVTYPERn, bits [63:0]:

When PMSELR_EL0.SEL == 31, this register accesses PMCCFILTR_EL0.

Otherwise, this register accesses PMEVTYPER<n>_EL0 where n is the value in PMSELR_EL0.SEL.

The reset behavior of this field is:

Access Instructions

If FEAT_FGT is implemented, and PMSELR_EL0.SEL is not 31 and is greater than or equal to the number of accessible event counters, then the behavior of permitted reads and writes of PMXEVTYPER_EL0 is as follows:

If FEAT_FGT is not implemented, and PMSELR_EL0.SEL is not 31 and is greater than or equal to the number of accessible event counters, then reads and writes of PMXEVTYPER_EL0 are CONSTRAINED UNPREDICTABLE, and the following behaviors are permitted:

Permitted reads and writes of PMXEVTYPER_EL0 are RAZ/WI if all of the following are true:

Permitted writes of PMXEVTYPER_EL0 are ignored if all of the following are true:

In EL0, an access is permitted if it is enabled by PMUSERENR_EL0.{UEN,EN}.

If EL2 is implemented and enabled in the current Security state, in EL1 and EL0, MDCR_EL2.HPMN identifies the number of accessible event counters.

Otherwise, the number of accessible event counters is determined by the Effective value of PMCCR.EPMN. For more information, see MDCR_EL2.HPMN and PMCCR.EPMN.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMXEVTYPER_EL0

(op0 = 0b11, op1 = 0b011, CRn = 0b1001, CRm = 0b1101, op2 = 0b001)

if !(IsFeatureImplemented(FEAT_PMUv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif UInt(PMSELR_EL0().SEL) != 31 && UInt(PMSELR_EL0().SEL) >= GetNumEventCountersSelfHosted() then if IsFeatureImplemented(FEAT_FGT) then Undefined(); else ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); end; elsif HaveEL(EL3) && PSTATE.EL != EL3 && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif PSTATE.EL == EL0 then if PMUSERENR_EL0().EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || PMUSERENR_EL0().UEN == '0') then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EL2Enabled() && EffectivelyAtEL0NotInHost() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMEVTYPERn_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && UInt(PMSELR_EL0().SEL) != 31 && UInt(PMSELR_EL0().SEL) >= GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); else AArch64_SystemAccessTrap(EL2, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0().UEN == '1' && ((UInt(PMSELR_EL0().SEL) != 31 && PMUACR_EL1()[UInt(PMSELR_EL0().SEL)] == '0') || (UInt(PMSELR_EL0().SEL) == 31 && PMUACR_EL1().C == '0')) then X{64}(t) = Zeros{64}; elsif UInt(PMSELR_EL0().SEL) == 31 then X{64}(t) = PMCCFILTR_EL0(); else X{64}(t) = PMEVTYPER_EL0(UInt(PMSELR_EL0().SEL)); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMEVTYPERn_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && UInt(PMSELR_EL0().SEL) != 31 && UInt(PMSELR_EL0().SEL) >= GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); else AArch64_SystemAccessTrap(EL2, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif UInt(PMSELR_EL0().SEL) == 31 then X{64}(t) = PMCCFILTR_EL0(); else X{64}(t) = PMEVTYPER_EL0(UInt(PMSELR_EL0().SEL)); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif UInt(PMSELR_EL0().SEL) == 31 then X{64}(t) = PMCCFILTR_EL0(); else X{64}(t) = PMEVTYPER_EL0(UInt(PMSELR_EL0().SEL)); end; elsif PSTATE.EL == EL3 then if UInt(PMSELR_EL0().SEL) == 31 then X{64}(t) = PMCCFILTR_EL0(); else X{64}(t) = PMEVTYPER_EL0(UInt(PMSELR_EL0().SEL)); end; end;

MSR PMXEVTYPER_EL0, <Xt>

(op0 = 0b11, op1 = 0b011, CRn = 0b1001, CRm = 0b1101, op2 = 0b001)

if !(IsFeatureImplemented(FEAT_PMUv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif UInt(PMSELR_EL0().SEL) != 31 && UInt(PMSELR_EL0().SEL) >= GetNumEventCountersSelfHosted() then if IsFeatureImplemented(FEAT_FGT) then Undefined(); else ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); end; elsif HaveEL(EL3) && PSTATE.EL != EL3 && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif PSTATE.EL == EL0 then if PMUSERENR_EL0().EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || PMUSERENR_EL0().UEN == '0') then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EL2Enabled() && EffectivelyAtEL0NotInHost() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMEVTYPERn_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && UInt(PMSELR_EL0().SEL) != 31 && UInt(PMSELR_EL0().SEL) >= GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); else AArch64_SystemAccessTrap(EL2, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0().UEN == '1' && ((UInt(PMSELR_EL0().SEL) != 31 && (PMUACR_EL1()[UInt(PMSELR_EL0().SEL)] == '0' || PMUSERENR_EL0().ER == '1')) || (UInt(PMSELR_EL0().SEL) == 31 && (PMUACR_EL1().C == '0' || PMUSERENR_EL0().CR == '1'))) then return; elsif UInt(PMSELR_EL0().SEL) == 31 then PMCCFILTR_EL0() = X{64}(t); else PMEVTYPER_EL0(UInt(PMSELR_EL0().SEL)) = X{64}(t); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMEVTYPERn_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && UInt(PMSELR_EL0().SEL) != 31 && UInt(PMSELR_EL0().SEL) >= GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); else AArch64_SystemAccessTrap(EL2, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif UInt(PMSELR_EL0().SEL) == 31 then PMCCFILTR_EL0() = X{64}(t); else PMEVTYPER_EL0(UInt(PMSELR_EL0().SEL)) = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif UInt(PMSELR_EL0().SEL) == 31 then PMCCFILTR_EL0() = X{64}(t); else PMEVTYPER_EL0(UInt(PMSELR_EL0().SEL)) = X{64}(t); end; elsif PSTATE.EL == EL3 then if UInt(PMSELR_EL0().SEL) == 31 then PMCCFILTR_EL0() = X{64}(t); else PMEVTYPER_EL0(UInt(PMSELR_EL0().SEL)) = X{64}(t); end; end;


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