Performance Monitors Snapshot Status and Capture Register
Holds status information about the captured counters and provides a mechanism for software to initiate a sample.
AArch64 System register PMSSCR_EL1 bits [63:0] are architecturally mapped to External register PMSSCR_EL1[63:0].
This register is present only when FEAT_PMUv3_SS is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to PMSSCR_EL1 are UNDEFINED.
PMSSCR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | NC | ||||||||||||||||||||||||||||||
| RES0 | SS | ||||||||||||||||||||||||||||||
Reserved, RES0.
No Capture. Indicates whether the PMU counters have been captured.
| NC | Meaning |
|---|---|
| 0b0 |
PMU counters captured. |
| 0b1 |
PMU counters not captured. |
The reset behavior of this field is:
Reserved, RES0.
Snapshot Capture and Status.
| SS | Meaning |
|---|---|
| 0b0 |
On a read, the Capture event has completed. |
| 0b1 | On a read, the Capture event has not completed. On a write, request a Capture event. |
A write of 0 to this field is ignored.
It is CONSTRAINED UNPREDICTABLE whether a Capture event has completed if this field is modified when the Capture event is ongoing.
The reset behavior of this field is:
Accessing this field has the following behavior:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, PMSSCR_EL1
(op0 = 0b11, op1 = 0b000, CRn = 0b1001, CRm = 0b1101, op2 = 0b011)
if !(IsFeatureImplemented(FEAT_PMUv3_SS) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPMSS == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGRTR2_EL2().nPMSSCR_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnPMSS == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMSSCR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MDCR_EL3().EnPMSS == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMSSCR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = PMSSCR_EL1(); end;
MSR PMSSCR_EL1, <Xt>
(op0 = 0b11, op1 = 0b000, CRn = 0b1001, CRm = 0b1101, op2 = 0b011)
if !(IsFeatureImplemented(FEAT_PMUv3_SS) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPMSS == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGWTR2_EL2().nPMSSCR_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnPMSS == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMSSCR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MDCR_EL3().EnPMSS == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMSSCR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then PMSSCR_EL1() = X{64}(t); end;
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