PMSIDR_EL1

This register is present only when FEAT_SPE is implemented. Otherwise, direct accesses to PMSIDR_EL1 are UNDEFINED.

Attributes

Field descriptions

Bits [63:33]:

SME, bit [32]:

SPE for SME. Describes support for the Scalable Matrix Extensions to Statistical Profiling.

The value of this field is an IMPLEMENTATION DEFINED choice of:

SME	Meaning
0b0	The SME extensions to the Statistical Profiling Extension are not implemented.
0b1	Adds support for Statistical Profiling of the Scalable Matrix Extensions.

FEAT_SPE_SME implements the functionality identified by the value 1.

Access to this field is RO.

ALTCLK, bits [31:28]:

Alternate clock domain.

The value of this field is an IMPLEMENTATION DEFINED choice of:

ALTCLK	Meaning
0b0000	Alternate clock domain not implemented, or CPU clock domain.
0b0001	The external Streaming Mode Compute Unit provides the alternate clock domain.
0b1111	IMPLEMENTATION DEFINED clock domain.

All other values are reserved.

FEAT_SPE_ALTCLK implements the functionality identified by a nonzero value.

Access to this field is RO.

FPF, bit [27]:

Floating-point flag. Describes whether Operation Type packets for sampled scalar and SIMD operations contain floating-point and Advanced SIMD indications.

The value of this field is an IMPLEMENTATION DEFINED choice of:

FPF	Meaning
0b0	Operation Type packets for scalar and Advanced SIMD operations do not contain floating-point or Advanced SIMD information.
0b1	Operation Type packets for scalar and Advanced SIMD operations contain floating-point or Advanced SIMD information.

FEAT_SPE_FPF implements the functionality identified by the value 1.

Access to this field is RO.

EFT, bit [26]:

Extended filtering by type. Describes whether Extended filtering by operation type is supported.

The value of this field is an IMPLEMENTATION DEFINED choice of:

EFT	Meaning
0b0	PMSFCR_EL1.{SIMDm, FPm, STm, Bm, LDm, SIMD, FP} are RES0.
0b1	PMSFCR_EL1.{SIMDm, FPm, STm, Bm, LDm, SIMD, FP} are implemented.

FEAT_SPE_EFT implements the functionality identified by the value 1.

Access to this field is RO.

CRR, bit [25]:

Call Return branch records. Describes whether the Operation Type packets for sampled branch operations contain Call Return information.

The value of this field is an IMPLEMENTATION DEFINED choice of:

CRR	Meaning
0b0	Operation Type packets for branch operations do not contain Call Return information.
0b1	Operation Type packets for branch operations contain Call Return information.

FEAT_SPE_CRR implements the functionality identified by the value 1.

Access to this field is RO.

PBT, bit [24]:

Previous branch target Address packet. Describes whether the Previous branch target Address packet is supported.

The value of this field is an IMPLEMENTATION DEFINED choice of:

PBT	Meaning
0b0	Previous branch target Address packet not implemented.
0b1	Previous branch target Address packet implemented.

FEAT_SPE_PBT implements the OPTIONAL functionality identified by the value 1.

Access to this field is RO.

Format, bits [23:20]:

Defines the format of the sample records.

Format	Meaning
0b0000	Format 0.

All other values are reserved.

Access to this field is RO.

CountSize, bits [19:16]:

Defines the size of the counters.

The value of this field is an IMPLEMENTATION DEFINED choice of:

CountSize	Meaning
0b0010	12-bit saturating counters.
0b0011	16-bit saturating counters.

All other values are reserved.

Access to this field is RO.

MaxSize, bits [15:12]:

Defines the largest size for a single record, rounded up to a power-of-two. If this is the same as the minimum alignment (PMBIDR_EL1.Align), then each record is exactly this size.

The value of this field is an IMPLEMENTATION DEFINED choice of:

MaxSize	Meaning
0b0100	16 bytes.
0b0101	32 bytes.
0b0110	64 bytes.
0b0111	128 bytes.
0b1000	256 bytes.
0b1001	512 bytes.
0b1010	1KB.
0b1011	2KB.

All other values are reserved.

The values 0b0100 and 0b0101 are not permitted for an implementation.

Access to this field is RO.

Interval, bits [11:8]:

Minimum sampling interval. This provides guidance from the implementer to the smallest sampling interval.

The interval is defined as a number of either operations or instructions, depending on the IMPLEMENTATION DEFINED value of PMSIDR_EL1.ArchInst.

The value of this field is an IMPLEMENTATION DEFINED choice of:

Interval	Meaning
0b0000	256 operations or instructions, or no minimum specified.
0b0010	512 operations or instructions.
0b0011	768 operations or instructions.
0b0100	1,024 operations or instructions.
0b0101	1,536 operations or instructions.
0b0110	2,048 operations or instructions.
0b0111	3,072 operations or instructions.
0b1000	4,096 operations or instructions.

All other values are reserved.

If this field reads as a nonzero value, then setting the sample interval to a value less than the indicated value is likely to cause a statistically significant number of sample collisions. For example, the smallest interval might indicate the typical size of the speculation window for the implementation. That is, the number of operations or instructions that will be executing in parallel, when the processor implementation is not heavily loaded.

Setting the sample interval to a value greater than or equal to the indicated value does not guarantee a statistically insignificant number of sample collisions, as this is typically dependent on the program being profiled. For example, if the program has a large number of long latency loads due to cache misses, then this might cause more collisions when these operations or instructions are sampled.

For more information, see 'Sample collisions'.

Access to this field is RO.

FDS, bit [7] when FEAT_SPEv1p4 is implemented:

Filtering by data source.

The value of this field is an IMPLEMENTATION DEFINED choice of:

FDS	Meaning
0b0	PMSDSFR_EL1 is not implemented and PMSFCR_EL1.FDS is RES0.
0b1	PMSDSFR_EL1 and PMSFCR_EL1.FDS are implemented.

FEAT_SPE_FDS implements the functionality identified by the value 1.

From Armv8.9, if FEAT_SPE_LDS is implemented, the value 0 is not permitted.

Access to this field is RO.

Otherwise:

FnE, bit [6] when FEAT_SPE_FnE is implemented:

Filtering by events, inverted.

The value of this field is an IMPLEMENTATION DEFINED choice of:

FnE	Meaning
0b0	PMSNEVFR_EL1 is not implemented and PMSFCR_EL1.FnE is RES0.
0b1	PMSNEVFR_EL1 and PMSFCR_EL1.FnE are implemented.

FEAT_SPE_FnE implements the functionality identified by the value 1.

From Armv8.7, if FEAT_SPE is implemented, the value 0 is not permitted.

Access to this field is RO.

Otherwise:

ERnd, bit [5]:

Defines how the random number generator is used in determining the interval between samples, when enabled by PMSIRR_EL1.RND.

The value of this field is an IMPLEMENTATION DEFINED choice of:

ERnd	Meaning
0b0	The random number is added at the start of the interval, and the sample is taken and a new interval started when the combined interval expires.
0b1	The random number is added and the new interval started after the interval programmed in PMSIRR_EL1.INTERVAL expires, and the sample is taken when the random interval expires.

FEAT_SPE_ERnd implements the functionality identified by the value 1.

Access to this field is RO.

LDS, bit [4]:

Data source indicator for sampled load instructions.

The value of this field is an IMPLEMENTATION DEFINED choice of:

LDS	Meaning
0b0	Loaded data source not implemented.
0b1	Loaded data source implemented.

FEAT_SPE_LDS implements the functionality identified by the value 1.

Access to this field is RO.

ArchInst, bit [3]:

Architectural instruction profiling. Defines the subject of the profiling population.

The value of this field is an IMPLEMENTATION DEFINED choice of:

ArchInst	Meaning
0b0	Micro-op sampling implemented.
0b1	Architecture instruction sampling implemented.

FEAT_SPE_ArchInst implements the functionality identified by the value 1.

Access to this field is RO.

FL, bit [2]:

Filtering by latency.

Reads as 0b1.

Access to this field is RO.

FT, bit [1]:

Filtering by operation type.

Reads as 0b1.

Access to this field is RO.

FE, bit [0]:

Filtering by events.

Reads as 0b1.

Access to this field is RO.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMSIDR_EL1

(op0 = 0b11, op1 = 0b000, CRn = 0b1001, CRm = 0b1001, op2 = 0b111)

if !IsFeatureImplemented(FEAT_SPE) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMSIDR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPMS == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMSIDR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMSIDR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = PMSIDR_EL1(); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																															SME
ALTCLK				FPF	EFT	CRR	PBT	Format				CountSize				MaxSize				Interval				FDS	FnE	ERnd	LDS	ArchInst	FL	FT	FE

Configuration

Attributes

Field descriptions

Bits [63:33]:

SME, bit [32]:

ALTCLK, bits [31:28]:

FPF, bit [27]:

EFT, bit [26]:

CRR, bit [25]:

PBT, bit [24]:

Format, bits [23:20]:

CountSize, bits [19:16]:

MaxSize, bits [15:12]:

Interval, bits [11:8]:

FDS, bit [7] when FEAT_SPEv1p4 is implemented:

Otherwise:

FnE, bit [6] when FEAT_SPE_FnE is implemented:

Otherwise:

ERnd, bit [5]:

LDS, bit [4]:

ArchInst, bit [3]:

FL, bit [2]:

FT, bit [1]:

FE, bit [0]:

Access Instructions