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PMSCR_EL1

Statistical Profiling Control Register (EL1)

Provides EL1 controls for Statistical Profiling.

Configuration

This register is present only when FEAT_SPE is implemented. Otherwise, direct accesses to PMSCR_EL1 are UNDEFINED.

Attributes

PMSCR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0EnVMKEEEPCTTSPACXRES0E1SPEE0SPE

Bits [63:12]:

Reserved, RES0.

EnVM, bit [11] when FEAT_SPE_nVM is implemented and FEAT_NV is implemented:

Reserved for software use in nested virtualization. See also PMSCR_EL2.EnVM.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

KE, bit [10] when FEAT_SPE_EXC is implemented:

Kernel exception enable for SPE Profiling exceptions taken to EL1.

KEMeaning
0b0

SPE Profiling exceptions taken to EL1 are always masked at EL1.

0b1

Enabled SPE Profiling exceptions taken to EL1 are masked at EL1 when PSTATE.PM is 1 and unmasked when PSTATE.PM is 0.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

EE, bits [9:8] when FEAT_SPE_EXC is implemented:

Exception Enable.

EEMeaningApplies when
0b00

Disabled. SPE Profiling exceptions for EL1 are disabled. All of the following apply:

  • Unless enabled by a higher Exception level, SPE Profiling exceptions are not generated.
  • PMBSR_EL1.S drives the interrupt request signal PMBIRQ.
  • Accesses to PMBSR_EL1 at EL1 ignore the value of HCR_EL2.NV1.
0b01

Reserved for software use in nested virtualization. Behaves as 0b00 for the purpose of controlling the SPE Profiling exception and interrupt request signal PMBIRQ, and as 0b11 for the purpose of accesses to PMBSR_EL1.

When FEAT_NV is implemented
0b10

Reserved for software use in nested virtualization. Behaves as 0b11 for the purposes of controlling the SPE Profiling exception and interrupt request signal PMBIRQ, and accesses to PMBSR_EL1.

When FEAT_NV is implemented
0b11

Enabled. SPE Profiling exceptions for EL1 are enabled, as follows:

  • All Profiling Buffer management events are recorded in PMBSR_EL1, unless they are configured to be recorded in PMBSR_EL3 by MDCR_EL3.PMSEE or PMBSR_EL2 by PMSCR_EL2.EE.
  • SPE Profiling exceptions are generated and taken to EL1 when unmasked and PMBSR_EL1.S is 1, unless the Effective value of HCR_EL2.TGE is 1, in which case the exception is taken to EL2.
  • The interrupt request signal PMBIRQ is not asserted.

For more information on the values reserved for software use in nested virtualization, see PMSCR_EL2.EE.

If the Effective value of PMSCR_EL2.EE is 0b00, then the Effective value of PMSCR_EL1.EE is 0b00.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

PCT, bits [7:6] when EL2 is implemented:

Physical Timestamp. If timestamp sampling is enabled and the Profiling Buffer owning Exception level is EL1, requests which timestamp counter value is collected.

If FEAT_ECV is implemented, this is a two-bit field as shown. Otherwise, bit[7] is RES0.

PCTMeaningApplies when
0b00

Virtual timestamp. The collected timestamp is the physical counter minus the value of CNTVOFF_EL2.

0b01

Physical timestamp. The collected timestamp is the physical counter.

0b11

Guest physical timestamp. The collected timestamp is the physical counter minus a physical offset. If any of the following are true, the physical offset is zero, otherwise the physical offset is the value of CNTPOFF_EL2:

When FEAT_ECV is implemented

When EL2 is implemented, all of the following apply:

The reset behavior of this field is:

Otherwise:

Physical Timestamp. Reserved. This field reads as 0b01 and ignores writes. Software should treat this field as UNK/SBZP.

When EL2 is not implemented, the Effective values of CNTVOFF_EL2 and CNTPOFF_EL2 are zero, meaning the virtual counter and physical counter have the same value.

TS, bit [5]:

Timestamp packet sample enable. Enables recording of Timestamp packets when the Profiling Buffer owning Exception level is EL1.

TSMeaning
0b0

Timestamp packet recording disabled.

0b1

Timestamp packet recording enabled.

If the Profiling Buffer owning Exception level is EL2, then this field is ignored by the PE. For more information, see Controlling the data that is collected.

When Timestamp packet recording is enabled, recording of End packets is disabled.

The reset behavior of this field is:

PA, bit [4]:

Physical Address packet sample enable. Enables recording of Physical Address packets when the Profiling Buffer owning Exception level is EL1.

PAMeaning
0b0

Physical Address packet recording disabled.

0b1

Physical Address packet recording is not disabled by this control.

When EL2 is implemented, all of the following apply:

For more information, see Controlling the data that is collected.

The reset behavior of this field is:

CX, bit [3]:

CONTEXTIDR_EL1 Context packet sample enable. Enables recording of Context packets containing the value of CONTEXTIDR_EL1.

CXMeaning
0b0

CONTEXTIDR_EL1 Context packet recording disabled.

0b1

CONTEXTIDR_EL1 Context packet recording enabled.

The PE ignores the value of this field and CONTEXTIDR_EL1 Context packets are not recorded when any of the following apply:

For more information, see Controlling the data that is collected.

The reset behavior of this field is:

Bit [2]:

Reserved, RES0.

E1SPE, bit [1]:

EL1 Statistical Profiling Enable.

E1SPEMeaning
0b0

Sampling disabled at EL1.

0b1

Sampling enabled at EL1.

If the Effective value of HCR_EL2.TGE is 1, then this field is ignored by the PE.

The reset behavior of this field is:

E0SPE, bit [0]:

EL0 Statistical Profiling Enable. Controls sampling at EL0 when the Effective value of HCR_EL2.TGE is 0 or if EL2 is disabled or not implemented.

E0SPEMeaning
0b0

Sampling disabled at EL0.

0b1

Sampling enabled at EL0.

If the Effective value of HCR_EL2.TGE is 1, then this field is ignored by the PE.

The reset behavior of this field is:

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMSCR_EL1

(op0 = 0b11, op1 = 0b000, CRn = 0b1001, CRm = 0b1001, op2 = 0b000)

if !IsFeatureImplemented(FEAT_SPE) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMSCR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPMS == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x828); else X{64}(t) = PMSCR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = PMSCR_EL2(); else X{64}(t) = PMSCR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = PMSCR_EL1(); end;

MSR PMSCR_EL1, <Xt>

(op0 = 0b11, op1 = 0b000, CRn = 0b1001, CRm = 0b1001, op2 = 0b000)

if !IsFeatureImplemented(FEAT_SPE) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMSCR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPMS == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x828) = X{64}(t); else PMSCR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then PMSCR_EL2() = X{64}(t); else PMSCR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then PMSCR_EL1() = X{64}(t); end;

When FEAT_VHE is implemented:

MRS <Xt>, PMSCR_EL12

(op0 = 0b11, op1 = 0b101, CRn = 0b1001, CRm = 0b1001, op2 = 0b000)

if !IsFeatureImplemented(FEAT_SPE) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X{64}(t) = NVMem(0x828); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMSCR_EL1(); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = PMSCR_EL1(); else Undefined(); end; end;

When FEAT_VHE is implemented:

MSR PMSCR_EL12, <Xt>

(op0 = 0b11, op1 = 0b101, CRn = 0b1001, CRm = 0b1001, op2 = 0b000)

if !IsFeatureImplemented(FEAT_SPE) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem(0x828) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMSCR_EL1() = X{64}(t); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then PMSCR_EL1() = X{64}(t); else Undefined(); end; end;

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