PMOVSSET_EL0

AArch64 System register PMOVSSET_EL0 bits [63:0] are architecturally mapped to AArch64 System register PMOVSCLR_EL0[63:0].

AArch64 System register PMOVSSET_EL0 bits [63:0] are architecturally mapped to External register PMOVS[63:0].

AArch64 System register PMOVSSET_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMOVSSET[31:0].

AArch64 System register PMOVSSET_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMOVSR[31:0].

AArch64 System register PMOVSSET_EL0 bits [31:0] are architecturally mapped to External register PMOVSCLR_EL0[31:0].

AArch64 System register PMOVSSET_EL0 bits [31:0] are architecturally mapped to External register PMOVSSET_EL0[31:0].

AArch64 System register PMOVSSET_EL0 bits [63:32] are architecturally mapped to External register PMOVSCLR_EL0[63:32] when FEAT_PMUv3p9 is implemented or FEAT_PMUv3_EXT64 is implemented.

AArch64 System register PMOVSSET_EL0 bits [63:32] are architecturally mapped to External register PMOVSSET_EL0[63:32] when FEAT_PMUv3p9 is implemented or FEAT_PMUv3_EXT64 is implemented.

This register is present only when FEAT_PMUv3 is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to PMOVSSET_EL0 are UNDEFINED.

Attributes

Field descriptions

Bits [63:33]:

F0, bit [32] when FEAT_PMUv3_ICNTR is implemented:

Unsigned overflow flag for PMICNTR_EL0 set. On writes, allows software to set the unsigned overflow flag for PMICNTR_EL0 to 1. On reads, returns the unsigned overflow flag for PMICNTR_EL0 overflow status.

F0	Meaning
0b0	PMICNTR_EL0 has not overflowed.
0b1	PMICNTR_EL0 has overflowed.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Accessing this field has the following behavior:

Access to this field is RAZ/WI if all the following are true:
- EL3 is implemented.
- PSTATE.EL != EL3.
- MDCR_EL3.EnPM2 == '0'.
Access to this field is RAZ/WI if all the following are true:
- EL0 is the current Exception level.
- PMUSERENR_EL0.UEN == '0' or PMUACR_EL1.F0 == '0'.
Access to this field is RAZ/WI if all the following are true:
- FEAT_FGT2 is implemented.
- EL2Enabled().
- PSTATE.EL IN {EL1, EL0}.
- HCR_EL2.[E2H,TGE] != '11'.
- (EL3 is implemented and SCR_EL3.FGTEn2 == '0') or (HDFGRTR2_EL2.nPMICFILTR_EL0 == '0' and HDFGWTR2_EL2.nPMICFILTR_EL0 == '0').
Access to this field is RAZ/WI if all the following are true:
- FEAT_FGT2 is implemented.
- EL2Enabled().
- EL0 is the current Exception level.
- HCR_EL2.[E2H,TGE] != '11'.
- (EL3 is implemented and SCR_EL3.FGTEn2 == '0') or HDFGRTR2_EL2.nPMICFILTR_EL0 == '0'.
- PMUSERENR_EL0.IR == '1'.
Access to this field is WO/RAZ if all the following are true:
- FEAT_FGT2 is implemented.
- EL2Enabled().
- PSTATE.EL IN {EL1, EL0}.
- HCR_EL2.[E2H,TGE] != '11'.
- (EL3 is implemented and SCR_EL3.FGTEn2 == '0') or HDFGRTR2_EL2.nPMICFILTR_EL0 == '0'.
Access to this field is RO if all the following are true:
- FEAT_FGT2 is implemented.
- EL2Enabled().
- PSTATE.EL IN {EL1, EL0}.
- HCR_EL2.[E2H,TGE] != '11'.
- (EL3 is implemented and SCR_EL3.FGTEn2 == '0') or HDFGWTR2_EL2.nPMICFILTR_EL0 == '0'.
Access to this field is RO if all the following are true:
- EL0 is the current Exception level.
- PMUSERENR_EL0.IR == '1'.
Otherwise, access to this field is W1S.

Otherwise:

C, bit [31]:

Unsigned overflow flag for PMCCNTR_EL0 set. On writes, allows software to set the unsigned overflow flag for PMCCNTR_EL0 to 1. On reads, returns the unsigned overflow flag for PMCCNTR_EL0 overflow status.

C	Meaning
0b0	PMCCNTR_EL0 has not overflowed.
0b1	PMCCNTR_EL0 has overflowed.

PMCR_EL0.LC controls whether an overflow is detected from unsigned overflow of PMCCNTR_EL0[31:0] or unsigned overflow of PMCCNTR_EL0[63:0].

The reset behavior of this field is:

On a Cold reset, when FEAT_PMUv3_EXTPMN is implemented, this field resets to an architecturally UNKNOWN value.
On a Warm reset, when FEAT_PMUv3_EXTPMN is not implemented, this field resets to an architecturally UNKNOWN value.

Accessing this field has the following behavior:

Access to this field is RAZ/WI if all the following are true:
- FEAT_PMUv3p9 is implemented.
- EL0 is the current Exception level.
- PMUSERENR_EL0.UEN == '1'.
- PMUACR_EL1.C == '0'.
Access to this field is RO if all the following are true:
- FEAT_PMUv3p9 is implemented.
- EL0 is the current Exception level.
- PMUSERENR_EL0.[UEN,CR] == '11'.
Otherwise, access to this field is W1S.

P<m>, bit [m], for m = 30 to 0:

Unsigned overflow flag for PMEVCNTR<m>_EL0 set. On writes, allows software to set the unsigned overflow flag for PMEVCNTR<m>_EL0 to 1. On reads, returns the unsigned overflow flag for PMEVCNTR<m>_EL0 overflow status.

P<m>	Meaning
0b0	PMEVCNTR<m>_EL0 has not overflowed.
0b1	PMEVCNTR<m>_EL0 has overflowed.

If FEAT_PMUv3p5 is implemented, MDCR_EL2.HLP and PMCR_EL0.LP control whether an overflow is detected from unsigned overflow of PMEVCNTR<m>_EL0[31:0] or unsigned overflow of PMEVCNTR<m>_EL0[63:0].

The reset behavior of this field is:

On a Cold reset, when FEAT_PMUv3_EXTPMN is implemented, this field resets to an architecturally UNKNOWN value.
On a Warm reset, when FEAT_PMUv3_EXTPMN is not implemented, this field resets to an architecturally UNKNOWN value.

Accessing this field has the following behavior:

When m >= GetNumEventCountersAccessible(), access to this field is RAZ/WI.
Access to this field is RAZ/WI if all the following are true:
- FEAT_PMUv3p9 is implemented.
- EL0 is the current Exception level.
- PMUSERENR_EL0.UEN == '1'.
- PMUACR_EL1.P<m> == '0'.
Access to this field is RO if all the following are true:
- FEAT_PMUv3p9 is implemented.
- EL0 is the current Exception level.
- PMUSERENR_EL0.[UEN,ER] == '11'.
Otherwise, access to this field is W1S.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMOVSSET_EL0

(op0 = 0b11, op1 = 0b011, CRn = 0b1001, CRm = 0b1110, op2 = 0b011)

if !(IsFeatureImplemented(FEAT_PMUv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL != EL3 && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif PSTATE.EL == EL0 then if PMUSERENR_EL0().EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || PMUSERENR_EL0().UEN == '0') then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EL2Enabled() && EffectivelyAtEL0NotInHost() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMOVS == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMOVSSET_EL0(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMOVS == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMOVSSET_EL0(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMOVSSET_EL0(); end; elsif PSTATE.EL == EL3 then X{64}(t) = PMOVSSET_EL0(); end;

MSR PMOVSSET_EL0, <Xt>

(op0 = 0b11, op1 = 0b011, CRn = 0b1001, CRm = 0b1110, op2 = 0b011)

if !(IsFeatureImplemented(FEAT_PMUv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL != EL3 && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif PSTATE.EL == EL0 then if PMUSERENR_EL0().EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || PMUSERENR_EL0().UEN == '0') then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EL2Enabled() && EffectivelyAtEL0NotInHost() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMOVS == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMOVSSET_EL0() = X{64}(t); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMOVS == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMOVSSET_EL0() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMOVSSET_EL0() = X{64}(t); end; elsif PSTATE.EL == EL3 then PMOVSSET_EL0() = X{64}(t); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																															F0
C	P30	P29	P28	P27	P26	P25	P24	P23	P22	P21	P20	P19	P18	P17	P16	P15	P14	P13	P12	P11	P10	P9	P8	P7	P6	P5	P4	P3	P2	P1	P0

Configuration

Attributes

Field descriptions

Bits [63:33]:

F0, bit [32] when FEAT_PMUv3_ICNTR is implemented:

Otherwise:

C, bit [31]:

P<m>, bit [m], for m = 30 to 0:

Access Instructions